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polyphase multifunction energy metering ic with harmonic monitoring data sheet ade7880 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011C2012 analog devices, inc. all rights reserved. features highly accurate; supports iec 62053-21, iec 62053-22, iec 62053-23, en 50470-1, en 50470-3, ansi c12.20, and ieee1459 standards supports iec 61000-4-7 class i and class ii accuracy specification compatible with 3-phase, 3- or 4-wire (delta or wye), and other 3-phase services supplies rms, active, reactive and apparent powers, power factor, thd, and harmonic distortion of all harmonics within 2.8 khz pass band on all phases supplies rms and harmonic distortions of all harmonics within 2.8 khz pass band on neutral current less than 1% error in harmonic current and voltage rms, harmonic active and reactive powers over a dynamic range of 2000 to 1 at t a = 25c supplies total (fundamental and harmonic) active and apparent energy and fundamental active/reactive energy on each phase and on the overall system less than 0.1% error in active and fundamental reactive energy over a dynamic range of 1000 to 1 at t a = 25c less than 0.2% error in active and fundamental reactive energy over a dynamic range of 5000 to 1 at t a = 25c less than 0.1% error in voltage and current rms over a dynamic range of 1000 to 1 at t a = 25c battery supply input for missing neutral operation wide-supply voltage operation: 2.4 v to 3.7 v reference: 1.2 v (drift 10 ppm/c typical) with external overdrive capability 40-lead lead frame chip scale package (lfcsp), pb-free, pin- for-pin compatible with ade7854 , ade7858 , ade7868 and ade7878 applications energy metering systems power quality monitoring solar inverters process monitoring protective devices general description the ade7880 1 is high accuracy, 3-phase electrical energy measurement ic with serial interfaces and three flexible pulse outputs. the ade7880 device incorporates second-order sigma- delta (-) analog-to-digital converters (adcs), a digital integrator, reference circuitry, and all of the signal processing required to perform the total (fundamental and harmonic) active, and apparent energy measurements, rms calculations, as well as fundamental-only active and reactive energy measurements. in addition, the ade7880 computes the rms of harmonics on the phase and neutral currents and on the phase voltages, together with the active, reactive and apparent powers, and the power factor and harmonic distortion on each harmonic for all phases. total harmonic distortion (thd) is computed for all currents and voltages. a fixed function digital signal processor (dsp) executes this signal processing. the dsp program is stored in the internal rom memory. the ade7880 is suitable for measuring active, reactive, and apparent energy in various 3-phase configurations, such as wye or delta services with, both, three and four wires. the ade7880 provides system calibration features for each phase, that is, rms offset correction, phase calibration, and gain calibration. the cf1, cf2, and cf3 logic outputs provide a wide choice of power information: total active powers, apparent powers, or the sum of the current rms values, and fundamental active and reactive powers. the ade7880 contains waveform sample registers that allow access to all adc outputs. the devices also incorporate power quality measurements, such as short duration low or high voltage detections, short duration high current variations, line voltage period measurement, and angles between phase voltages and currents. two serial interfaces, spi and i 2 c, can be used to communicate with the ade7880 . a dedicated high speed interface, the high speed data capture (hsdc) port, can be used in conjunction with i 2 c to provide access to the adc outputs and real-time power information. the ade7880 also has two interrupt request pins, irq0 and irq1 , to indicate that an enabled interrupt event has occurred. three specially designed low power modes ensure the continuity of energy accumulation when the is in a tampering situation. the is available in the 40-lead lfcsp, pb-free package, pin-for-pin compatible with , , , and devices. ade7880 ade7880 ade7854 ade7858 ade7868 ade7878 1 patents pending.
ade7880 data sheet rev. a | page 2 of 104 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? functional block diagram .............................................................. 3 ? specifications..................................................................................... 4 ? timing characteristics ................................................................ 7 ? absolute maximum ratings.......................................................... 10 ? thermal resistance .................................................................... 10 ? esd caution................................................................................ 10 ? pin configuration and function descriptions........................... 11 ? typical performance characteristics ........................................... 13 ? test circuit ...................................................................................... 18 ? terminology .................................................................................... 19 ? power management........................................................................ 20 ? psm0normal power mode (all parts)................................ 20 ? psm1reduced power mode.................................................. 20 ? psm2low power mode ......................................................... 20 ? psm3sleep mode (all parts) ................................................ 21 ? power-up procedure.................................................................. 23 ? hardware reset........................................................................... 24 ? software reset functionality .................................................... 24 ? theory of operation ...................................................................... 25 ? analog inputs.............................................................................. 25 ? analog-to-digital conversion.................................................. 25 ? current channel adc............................................................... 26 ? di/dt current sensor and digital integrator............................... 28 ? voltage channel adc ............................................................... 29 ? changing phase voltage data path.......................................... 30 ? power quality measurements................................................... 31 ? phase compensation ................................................................. 36 ? reference circuit........................................................................ 38 ? digital signal processor............................................................. 38 ? root mean square measurement............................................. 39 ? active power calculation .......................................................... 43 ? fundamental reactive power calculation.............................. 49 ? apparent power calculation..................................................... 53 ? power factor calculation .......................................................... 55 ? harmonics calculations............................................................ 56 ? waveform sampling mode ....................................................... 64 ? energy-to-frequency conversion............................................ 64 ? no load condition .................................................................... 69 ? checksum register..................................................................... 71 ? interrupts..................................................................................... 72 ? serial interfaces .......................................................................... 73 ? ade7880 quick setup as energy meter ................................ 80 ? ade7880 evaluation board...................................................... 80 ? die version.................................................................................. 80 ? silicon anomaly ............................................................................. 81 ? ade7880 functionality issues ................................................. 81 ? functionality issues.................................................................... 81 ? section 1. ade7880 functionality issues ............................... 82 ? registers list ................................................................................... 83 ? outline dimensions ..................................................................... 103 ? ordering guide ........................................................................ 103 ? revision history 3/12rev. 0 to rev. a removed references to + n (plus noise) and changed vthdn to vthd and ithdn to ithd.................................. throughout changes to reactive energy management parameter in table 1 .... 4 changes to figure 6........................................................................ 11 changes to table 7.......................................................................... 12 changes to phase compensation section ................................... 36 changes to equation 13 ................................................................. 39 changes to equation 33 ................................................................. 49 changes to fundamental reactive energy calculation section ... 51 changes to figure 80...................................................................... 55 changes to figure 85...................................................................... 62 changes to energy registers and cf outputs for various accumulation modes section....................................................... 67 changes to figure 95...................................................................... 69 changes to no load condition section...................................... 69 changes to equation 53................................................................. 71 changes to figure 100 ................................................................... 74 changes to figure 101 and to figure 102.................................... 75 changes to spi-compatible interface section ........................... 76 changes to hsdc interface section............................................ 78 changes to figure 109 and to figure 110.................................... 80 changes to silicon anomaly section........................................... 81 changes to table 48 ....................................................................... 99 changes to table 52 ..................................................................... 101 10/11revision 0: initial version
data sheet ade7880 rev. a | page 3 of 104 functional block diagram pga1 pga1 pga1 pga3 pga3 pga3 avgain aphcal hpf nigain hpfen of config3 digital integrator hpf aigain hpf por ldo ldo x 2 airms lpf x 2 x 2 avrms lpf lpf apgain lpf nirms nirmsos apgain afvaros apgain afwattos apgain awattos avrmsos 2 7 airmsos 2 7 dfc cf1den : dfc cf2den : dfc cf3den : 5 24 26 25 17 4 7 8 9 22 12 13 14 19 18 39 37 38 36 32 29 35 34 33 3 2 27 28 23 6 reset ref in/out vdd agnd avdd dvdd dgnd clkin clkout iap ian vap ibp ibn vbp icp icn vcp vn pm0 pm1 cf1 cf2/hready cf3/hsclk irq0 irq1 sclk/scl mosi/sda miso/hsd ss/hsa hsdc i 2 c spi/i 2 c ade7880 adc adc adc adc adc adc pga2 15 16 inp inn adc total/fundamental active energies fundamental reactive energy apparent energy voltage current rms harmonic information calculation for phase b (see phase a for detailed data path) total/fundamental active energies fundamental reactive energy apparent energy voltage/current rms harmonic information calculation for phase c (see phase a for detailed data path) computational block for harmonic information on neutral current digital signal processor computational block for harmonic information on phase a current and voltage computational block for fundamental active and reactive power phase a, phase b, and phase c data hpfen of config3 hpfen of config3 digital integrator 1.2v ref 10193-001 figure 1. ade7880 functional block diagram
ade7880 data sheet rev. a | page 4 of 104 specifications vdd = 3.3 v 10%, agnd = dgnd = 0 v, on-chip reference, clkin = 16.384 mhz, t min to t max = ?40c to +85c. table 1. parameter 1 , 2 min typ max unit test conditions/comments active energy measurement active energy measurement error (per phase) total active energy 0.1 % over a dynamic range of 1000 to 1, pga = 1, 2, 4; integrator off, pf = 1, gain compensation only 0.2 % over a dynamic range of 5000 to 1, pga = 1, 2, 4; integrator off, pf = 1 0.1 % over a dynamic range of 500 to 1, pga = 8, 16; integrator on, pf = 1, gain compensation only 0.2 % over a dynamic range of 2000 to 1, pga = 8, 16; integrator on, pf = 1 fundamental active energy 0.1 % over a dynamic range of 1000 to 1, pga = 1, 2, 4; integrator off, pf = 1, gain compensation only 0.2 % over a dynamic range of 5000 to 1, pga = 1, 2, 4; integrator off, pf = 1 0.1 % over a dynamic range of 500 to 1, pga = 8, 16; integrator on, pf = 1, gain compensation only 0.2 % over a dynamic range of 2000 to 1, pga = 8, 16; integrator on, pf = 1 phase error between channels line frequency = 45 hz to 65 hz, hpf on power factor (pf) = 0.8 capacitive 0.05 degrees phase lead 37 pf = 0.5 inductive 0.05 degrees phase lag 60 ac power supply rejection vdd = 3.3 v + 120 mv rms/120 hz, ipx = vpx = 100 mv rms output frequency variation 0.01 % dc power supply rejection vdd = 3.3 v 330 mv dc output frequency variation 0.01 % total active energy measurement bandwidth (?3 db) 3.3 khz reactive energy measurement reactive energy measurement error (per phase) fundamental reactive energy 0.1 % over a dynamic range of 1000 to 1, pga = 1, 2, 4; integrator off, pf = 0, gain compensation only 0.2 % over a dynamic range of 5000 to 1, pga = 1, 2, 4; integrator off, pf = 0 0.1 % over a dynamic range of 500 to 1, pga = 8, 16; integrator on, pf = 0, gain compensation only 0.2 % over a dynamic range of 2000 to 1, pga = 8, 16; integrator on, pf = 0 phase error between channels line frequency = 45 hz to 65 hz, hpf on pf = 0.8 capacitive 0.05 degrees phase lead 37 pf = 0.5 inductive 0.05 degrees phase lag 60 ac power supply rejection vdd = 3.3 v + 120 mv rms/120 hz, ipx = vpx = 100 mv rms output frequency variation 0.01 % dc power supply rejection vdd = 3.3 v 330 mv dc
data sheet ade7880 rev. a | page 5 of 104 parameter 1 , 2 min typ max unit test conditions/comments output frequency variation 0.01 % fundamental reactive energy measurement bandwidth (?3 db) 3.3 khz rms measurements i rms and v rms measurement bandwidth (?3 db) 3.3 khz i rms and v rms measurement error (psm0 mode) 0.1 % over a dynamic range of 1000 to 1, pga = 1 mean absolute value (mav) measurement i mav measurement bandwidth (psm1 mode) 260 hz i mav measurement error (psm1 mode) 0.5 % over a dynamic range of 100 to 1, pga = 1, 2, 4, 8 harmonic measurements bandwidth (?3 db) 3.3 khz no attenuation pass band 2.8 khz fundamental line frequency f l 45 66 hz nominal voltages must have amplitudes greater than 100 mv peak at voltage adcs maximum number of harmonics 3 ? ? ? ? ? ? l f 2800 absolute maximum number of harmonics 63 harmonic rms measurement error 1 % instantaneous reading accuracy over a dynamic range of 1000 to 1 for harmonics of frequencies within the pass band; after the initial 750 ms settling time; pga = 1 accuracy over a dynamic range of 2000:1 for harmonics of frequencies within the pass band; average of 10 readings at 128 ms update rate, after the initial 750 ms setting time; pga = 1 harmonic active/reactive power measurement error 1 % instantaneous reading accuracy over a dynamic range of 1000 to 1 for harmonics of frequencies within the pass band; after the initial 750 ms settling time; pga = 1. accuracy over a dynamic range of 2000:1 for harmonics of frequencies within the pass band; average of 5 readings at 128 ms update rate, after the initial 750 ms setting time; pga = 1. analog inputs maximum signal levels 500 mv peak differential inputs between the following pins: iap and ian, ibp and ibn, icp and icn; single-ended inputs between the following pins: vap and vn, vbp and vn, vcp, and vn input impedance (dc) iap, ian, ibp, ibn, icp, icn, vap, vbp, and vcp pins 490 k vn pin 170 k adc offset error ?35 mv pga = 1, uncalibrated error, see the terminology section. scales inversely proportional to the other pga gains. gain error ?2 % external 1.2 v reference
ade7880 data sheet rev. a | page 6 of 104 parameter 1 , 2 min typ max unit test conditions/comments waveform sampling sampling clkin/2048, 16.384 mhz/2048 = 8 ksps current and voltage channels see the waveform sampling mode section signal-to-noise ratio, snr 72 db pga = 1 signal-to-noise-and-distortion ratio, sinad 72 db pga = 1 bandwidth (?3 db) 3.3 khz time interval between phases measurement error 0.3 degrees line frequency = 45 hz to 65 hz, hpf on cf1, cf2, cf3 pulse outputs maximum output frequency 68.818 khz wthr = varthr = vathr = 3 duty cycle 50 % if cf1, cf2, or cf3 frequency > 6.25 hz and cfden is even and > 1 (1 + 1/cfden) 50 % if cf1, cf2, or cf3 frequency > 6.25 hz and cfden is odd and > 1 active low pulse width 80 ms if cf 1, cf2, or cf3 frequency < 6.25 hz jitter 0.04 % for cf1, cf2, or cf3 frequency = 1 hz and nominal phase currents are larger than 10% of full scale reference input ref in/out input voltage range 1.1 1.3 v minimum = 1.2 v ? 8%; maximum = 1.2 v + 8% input capacitance 10 pf on-chip reference nominal 1.21 v at the ref in/out pin at t a = 25c psm0 and psm1 modes reference error 2 mv output impedance 1 k temperature coefficient 10 50 ppm/c clkin all specifications clkin of 16.384 mhz input clock frequency 16.22 16.384 16.55 mhz crystal equivalent series resistance 30 200 clkin load capacitor 4 20 40 pf clkout load capacitor 4 20 40 pf logic inputsmosi/sda, sclk/scl, ss , reset , pm0, and pm1 input high voltage, v inh 2.4 v vdd = 3.3 v 10% input current, i in 82 na input = vdd = 3.3 v input low voltage, v inl 0.8 v vdd = 3.3 v 10% input current, i in ?7.3 a input = 0, vdd = 3.3 v input capacitance, c in 10 pf logic outputs irq0 , irq1 , and miso/hsd vdd = 3.3 v 10% output high voltage, v oh 3.0 v vdd = 3.3 v 10% i source 800 a output low voltage, v ol 0.4 v vdd = 3.3 v 10% i sink 2 ma cf1, cf2, cf3/hsclk output high voltage, v oh 2.4 v vdd = 3.3 v 10% i source 500 a output low voltage, v ol 0.4 v vdd = 3.3 v 10% i sink 2 ma
data sheet ade7880 rev. a | page 7 of 104 parameter 1 , 2 min typ max unit test conditions/comments power supply for specified performance psm0 mode vdd pin 2.97 3.63 v mini mum = 3.3 v ? 10%; maximum = 3.3 v + 10% i dd 25 28 ma psm1 and psm2 modes vdd pin 2.4 3.7 v i dd psm1 mode 5.3 5.8 ma psm2 mode 0.2 0.27 ma psm3 mode for specified performance vdd pin 2.4 3.7 v i dd in psm3 mode 1.8 6 a 1 see the typical performance characteristics section. 2 see the terminology section for a definition of the parameters. 3 ? ? ? ? ? ? l f 2800 means the whole number of the division. 4 the clkin/clkout load capacitors refer to the capacitors that are mounted between the clkin and clkout pins of the ade7880 and agnd. the capacitors should be chosen based on the crystal manufacturers data sheet specification, and they must not have more than the maximum value spec ified in the table. timing characteristics vdd = 3.3 v 10%, agnd = dgnd = 0 v, on-chip reference, clkin = 16.384 mhz, t min to t max = ?40c to +85c. note that dual function pin names are referenced by the relevant function only within the timing tables and diagrams (see the pin configuration and function descriptions section for full pin mnemonics and descriptions). table 2. i 2 c-compatible interface timing parameter standard mode fast mode parameter symbol min max min max unit scl clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition t hd;sta 4.0 0.6 s low period of scl clock t low 4.7 1.3 s high period of scl clock t high 4.0 0.6 s set-up time for repeated start condition t su;sta 4.7 0.6 s data hold time t hd;dat 0 3.45 0 0.9 s data setup time t su;dat 250 100 ns rise time of both sda and scl signals t r 1000 20 300 ns fall time of both sda and scl signals t f 300 20 300 ns setup time for stop condition t su;sto 4.0 0.6 s bus free time between a stop and start condition t buf 4.7 1.3 s pulse width of suppressed spikes t sp n/a 1 50 ns 1 n/a means not applicable.
ade7880 data sheet rev. a | page 8 of 104 t f t f t hd;dat t hd;sta t high t su;sta t su;dat t f t hd;sta t sp t su;sto t f t buf t low sda sclk start condition repeated start condition stop condition start condition 10193-002 figure 2. i 2 c-compatible in terface timing table 3. spi interface timing parameters parameter symbol min max unit ss to sclk edge t ss 50 ns sclk period 0.4 4000 1 s sclk low pulse width t sl 175 ns sclk high pulse width t sh 175 ns data output valid after sclk edge t dav 100 ns data input setup time before sclk edge t dsu 100 ns data input hold time after sclk edge t dhd 5 ns data output fall time t df 20 ns data output rise time t dr 20 ns sclk rise time t sr 20 ns sclk fall time t sf 20 ns miso disable after ss rising edge t dis 200 ns ss high after sclk edge t sfs 0 ns 1 guaranteed by design. msb lsb lsb in intermediate bits intermediate bits t sfs t dis t ss t sl t df t sh t dhd t dav t dsu t sr t sf t dr msb in mosi miso sclk ss 10193-003 figure 3. spi interface timing
data sheet ade7880 rev. a | page 9 of 104 table 4. hsdc interface timing parameter parameter symbol min max unit hsa to hsclk edge t ss 0 ns hsclk period 125 ns hsclk low pulse width t sl 50 ns hsclk high pulse width t sh 50 ns data output valid after hsclk edge t dav 40 ns data output fall time t df 20 ns data output rise time t dr 20 ns hsclk rise time t sr 10 ns hsclk fall time t sf 10 ns hsd disable after hsa rising edge t dis 5 ns hsa high after hsclk edge t sfs 0 ns msb lsb intermediate bits t sfs t dis t ss t sl t df t sh t dav t sr t sf t dr hsd hsclk hsa 10193-004 figure 4. hsdc interface timing 2ma i ol 800a i oh 1.6v to output pin c l 50pf 10193-005 figure 5. load circuit for timing specifications
ade7880 data sheet rev. a | page 10 of 104 absolute maximum ratings t a = 25c, unless otherwise noted. table 5. parameter 1 rating vdd to agnd ?0.3 v to +3.7 v vdd to dgnd ?0.3 v to +3.7 v analog input voltage to agnd, iap, ian, ibp, ibn, icp, icn, vap, vbp, vcp, vn ?2 v to +2 v analog input voltage to inp and inn ?2 v to +2 v reference input voltage to agnd ?0.3 v to vdd + 0.3 v digital input voltage to dgnd ?0.3 v to vdd + 0.3 v digital output voltage to dgnd ?0.3 v to vdd + 0.3 v operating temperature industrial range ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c lead temperature (soldering, 10 sec) 300c 1 regarding the temperature profile used in soldering rohs compliant parts, analog devices, inc. advises that reflow profiles should conform to j-std 20 from jedec. refer to jedec website for the latest revision. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified equal to 29.3c/w; jc is specified equal to 1.8c/w. table 6. thermal resistance package type ja jc unit 40-lead lfcsp 29.3 1.8 c/w esd caution
data sheet ade7880 rev. a | page 11 of 104 pin configuration and fu nction descriptions notes 1. nc = no connect. 2. create a similar pad on the pcb under the exposed pad. solder the exposed pad to the pad on the pcb to confer mechanical strength to the package. do not connect the pads to agnd or dgnd. 11 nc 12 ibn 13 icp 15 inp 17 ref in/out 16 in n 18 vn 19 vcp 20 nc 14 icn nc pm0 pm1 reset dvdd dgnd iap ian ibp nc vap avdd agnd vdd clkin clkout irq0 nc vbp nc 33 cf1 34 cf2/hread y 35 cf3 /hsclk 36 sclk/scl 37 miso/hsd 38 mosi/sda 39 ss/hsa 40 n c 32 irq1 31 nc 1 2 3 4 5 6 7 8 9 10 23 24 25 26 27 28 29 30 22 21 ade7880 top view (not to scale) 10193-006 figure 6. pin configuration table 7. pin function descriptions pin no. mnemonic description 1, 10, 11, 20, 21, 30, 31, 40 nc no connect. do not connect to these pins. these pins are not connected internally. 2 pm0 power mode pin 0. this pin, combined with pm1, defines the power mode of the ade7880 , as described in table 8 . 3 pm1 power mode pin 1. this pin defines the power mode of the ade7880 when combined with pm0, as described in table 8 . 4 reset reset input, active low. in psm0 mode, this pi n should stay low for at least 10 s to trigger a hardware reset. 5 dvdd this pin provides access to the on-chip 2.5 v di gital ldo. do not connect any external active circuitry to this pin. decouple this pin with a 4.7 f capacitor in parallel with a ceramic 220 nf capacitor. 6 dgnd ground reference. this pin provides the ground reference for the digital circuitry. 7, 8 iap, ian analog inputs for current channel a. this channe l is used with the current transducers and is referenced in this data sheet as current channel a. these inputs are fully differential voltage inputs with a maximum differential level of 0.5 v. this channel also has an internal pga equal to the ones on channel b and channel c. 9, 12 ibp, ibn analog inputs for current channel b. this channe l is used with the current transducers and is referenced in this data sheet as current channel b. these inputs are fully differential voltage inputs with a maximum differential level of 0.5 v. this channel also has an internal pga equal to the ones on channel c and channel a. 13, 14 icp, icn analog inputs for current channel c. this channe l is used with the current transducers and is referenced in this data sheet as current channel c. these inputs are fully differential voltage inputs with a maximum differential level of 0.5 v. this channel also has an internal pga equal to the ones on channel a and channel b. 15, 16 inp, inn analog inputs for neutral current channel n. this channel is used with the current transducers and is referenced in this data sheet as current channel n. these inputs are fully differential voltage inputs with a maximum differential level of 0.5 v. this channel also has an internal pga, different from the ones found on the a, b, and c channels. 17 ref in/out this pin provides access to the on-chip voltage reference. the on-chip reference has a nominal value of 1.2 v. an external reference source with 1.2 v 8% can also be connected at this pin. in either case, decouple this pin to agnd with a 4.7 f capacitor in parallel with a ceramic 100 nf capacitor. after reset, the on-chip reference is enabled.
ade7880 data sheet rev. a | page 12 of 104 pin no. mnemonic description 18, 19, 22, 23 vn, vcp, vbp, vap analog inputs for the voltage channel. this cha nnel is used with the voltage transducer and is referenced as the voltage channel in this data sh eet. these inputs are single-ended voltage inputs with a maximum signal level of 0.5 v with respec t to vn for specified operation. this channel also has an internal pga. 24 avdd this pin provides access to the on-chip 2.5 v an alog low dropout regulator (ldo). do not connect external active circuitry to this pin. decouple this pin with a 4.7 f capacitor in parallel with a ceramic 220 nf capacitor. 25 agnd ground reference. this pin provides the ground reference for the analog circuitry. tie this pin to the analog ground plane or to the quietest ground reference in th e system. use this quiet ground reference for all analog circuitry, for example, antialiasing filters, current, and voltage transducers. 26 vdd supply voltage. this pin provides the supply volt age. in psm0 (normal power mode), maintain the supply voltage at 3.3 v 10% for specified operat ion. in psm1 (reduced power mode), psm2 (low power mode), and psm3 (sleep mode), when the ade7880 is supplied from a battery, maintain the supply voltage between 2.4 v and 3.7 v. decouple this pin to dgnd with a 10 f capacitor in parallel with a ceramic 100 nf capacitor. 27 clkin master clock. an external clock can be provided at this logic input. alternatively, a parallel resonant at-cut crystal can be connected across clkin an d clkout to provide a clock source for the ade7880 . the clock frequency for specified operation is 16.384 mhz. use ceramic load capacitors of a few tens of picofarad with the gate oscillator circ uit. refer to the crystal manufacturers data sheet for load capacitance requirements. 28 clkout a crystal can be connected across this pin and clkin (as previously described with pin 27 in this table) to provide a clock source for the ade7880 . 29, 32 irq0 , irq1 interrupt request outputs. these are active low logic outputs. see the interrupts section for a detailed presentation of the even ts that can trigger interrupts. 33, 34, 35 cf1, cf2/hready, cf3/hsclk calibration frequency (cf) logic outputs. these outputs provide power information based on the cf1sel[2:0], cf2sel[2:0], and cf3sel[2:0] bits in the cfmode register. these outputs are used for operational and calibration purposes. the full-scale output frequency can be scaled by writing to the cf1den, cf2den, and cf3den registers, respectively (see the energy-to-frequency conversion section). cf2 is multiplexed with the hready signal generated by the harmonic calculations block. cf3 is multiplexed with the serial clock output of the hsdc port. 36 sclk/scl serial clock input for spi port/serial clock input for i 2 c port. all serial data tr ansfers are synchronized to this clock (see the serial interfaces section). this pin has a schmid t trigger input for use with a clock source that has a slow edge transition time, for example, opto-isolator outputs. 37 miso/hsd data out for spi port/data out for hsdc port. 38 mosi/sda data in for spi port/data out for i 2 c port. 39 ss /hsa slave select for spi port/hsdc port active. ep exposed pad create a similar pad on the pcb under the exposed pad. solder the exposed pad to the pad on the pcb to confer mechanical strength to the packag e. do not connect the pads to agnd or dgnd.
data sheet ade7880 rev. a | page 13 of 104 typical performance characteristics 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) +25c, pf = 1.0 ?40c, pf = 1.0 +85c, pf = 1.0 10193-100 figure 7. total active energy error as percentage of reading (gain = +1, power factor = 1) over temperature with internal reference and integrator off 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) gain = +1 gain = +2 gain = +4 gain = +8 gain = +16 10193-101 figure 8. total active energy error as percentage of reading over gain with internal reference and integrator off 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 45 47 49 51 53 55 57 59 61 63 65 error (%) line frequency (hz) pf = +1.0 pf = +0.5 pf = ?0.5 10193-102 figure 9. total active energy error as percentage of reading (gain = +1) over frequency with internal reference and integrator off 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) v dd = 2.97v v dd = 3.30v v dd = 3.63v 10193-103 figure 10. total active energy error as percentage of reading (gain = +1) over power supply with internal reference and integrator off 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) +25c, pf = 1.0 ?40c, pf = 1.0 +85c, pf = 1.0 10193-104 figure 11. total active energy error as percentage of reading (gain = +16) over temperature with internal reference and integrator on 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) +25c, pf = 1.0 ?40c, pf = 1.0 +85c, pf = 1.0 10193-105 figure 12. fundamental active energy error as percentage of reading (gain = +1, power factor = 1) over temperature with internal reference and integrator off
ade7880 data sheet rev. a | page 14 of 104 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) gain = +1 gain = +2 gain = +4 gain = +8 gain = +16 10193-106 figure 13. fundamental active energy error as percentage of reading over gain with internal refe rence and integrator off 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) v dd = 2.97v v dd = 3.30v v dd = 3.63v 10193-107 figure 14. fundamental active energy error as percentage of reading (gain = +1) over power supply with internal reference and integrator off 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) +25c, pf = 1.0 ?40c, pf = 1.0 +85c, pf = 1.0 10193-108 figure 15. fundamental active energy error as percentage of reading (gain = +1) over temperature with internal reference and integrator on 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) +25c, pf = 1.0 ?40c, pf = 1.0 +85c, pf = 1.0 10193-109 figure 16. fundamental reactive energy error as percentage of reading (gain = +1, power factor = 0) over temperature with internal reference and integrator off 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) gain = +1 gain = +2 gain = +4 gain = +8 gain = +16 10193-110 figure 17. fundamental reactive energy error as percentage of reading over gain with internal refe rence and integrator off 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 45 47 49 51 53 55 57 59 61 63 65 error (%) line frequency (hz) pf = +1.0 pf = +0.5 pf = ?0.5 10193-111 figure 18. fundamental reactive energy error as percentage of reading (gain = +1) over frequency with internal reference and integrator off
data sheet ade7880 rev. a | page 15 of 104 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) v dd = 2.97v v dd = 3.30v v dd = 3.63v 10193-112 figure 19. fundamental reactive energy error as percentage of reading (gain = +1) over power supply with internal reference and integrator off 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) +25c, pf = 1.0 ?40c, pf = 1.0 +85c, pf = 1.0 10193-113 figure 20. fundamental reactive energy error as percentage of reading (gain = +16) over temperature with internal reference and integrator on 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) +25c, pf = 1.0 ?40c, pf = 1.0 +85c, pf = 1.0 10193-114 figure 21. i rms error as percentage of reading (gain = +1) over temperature with internal reference and integrator off 0.5 ?0.5 ?0.3 ?0.1 0.1 0.3 0.01 0.1 1 10 100 error (%) percentage of full-scale current (%) +25c, pf = 1.0 ?40c, pf = 1.0 +85c, pf = 1.0 10193-115 figure 22. v rms error as a percentage of reading (gain = +1) over temperature with internal reference 5 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 06 60575451484542393633 30 272421181512 963 gain error (% error relative to fundamental) harmonic order (55hz fundamental) 3 10193-116 figure 23. harmonic i rms error as a percentage of reading over harmonic order, 63 harmonics, 55 hz fundamental, 30 averages per reading, 750 ms settling time, 125 s update rate 6 ?6 ?4 ?2 0 2 4 0.01 0.1 1 10 100 measurement error (% of reading) percentage of full-scale current (%) 10193-117 figure 24. harmonic i rms error as a percentage of reading (gain = +1), 51 harmonics, 55 hz fundamental, single reading, 750 ms settling time
ade7880 data sheet rev. a | page 16 of 104 6 ?6 ?4 ?2 0 2 4 0.01 0.1 1 10 100 measurement error (% of reading) percentage of full-scale current (%) 10193-118 figure 25. harmonic i rms error as percentage of reading (gain = +1), 51 harmonics, 55 hz fundamental, 10 averages per reading, 750 ms settling time, 125 s update rate 6 ?6 ?4 ?2 0 2 4 0.01 0.1 1 10 100 measurement error (% of reading) percentage of full-scale current (%) 10193-119 figure 26. harmonic active power error as percentage of reading (gain = +1), 51 harmonics, 55 hz fundamental, single reading, 750 ms settling time, 125 s update rate 6 ?6 ?4 ?2 0 2 4 0.01 0.1 1 10 100 measurement error (% of reading) percentage of full-scale current (%) 10193-120 figure 27. harmonic active power error as percentage of reading (gain = +1), 51 harmonics, 55 hz fundamental, 10 averages per reading, 750 ms settling time, 125 s update rate 6 ?6 ?4 ?2 0 2 4 0.01 0.1 1 10 100 measurement error (% of reading) percentage of full-scale current (%) 10193-121 figure 28. harmonic reactive power error as percentage of reading (gain = +1), 51 harmonics, 55 hz fundamental, single reading, 750 ms settling time, 125 s update rate 6 ?6 ?4 ?2 0 2 4 0.01 0.1 1 10 100 measurement error (% of reading) percentage of full-scale current (%) 10193-122 figure 29. harmonic reactive power error as percentage of reading (gain = +1), 51 harmonics, 55 hz fundamental, 10 averages per reading, 750 ms settling time, 125 s update rate 6 ?6 ?4 ?2 0 2 4 0.01 0.1 1 10 100 measurement error (% of reading) percentage of full-scale current (%) 10193-123 figure 30. harmonic apparent power error as percentage of reading (gain = +1), 51 harmonics, 55 hz fundamental, single reading, 750 ms settling time, 125 s update rate
data sheet ade7880 rev. a | page 17 of 104 6 ?6 ?4 ?2 0 2 4 0.01 0.1 1 10 100 measurement error (% of reading) percentage of full-scale current (%) 10193-124 figure 31. harmonic apparent power error as percentage of reading (gain = +1), 51 harmonics, 55 hz fundamental, 10 averages per reading, 750 ms settling time, 125 s update rate
ade7880 data sheet rev. a | page 18 of 104 test circuit same as cf2 pm0 0.22f 4.7f mosi/sda miso/hsd sclk/scl cf3/hsclk cf2/hready cf1 ref in/out clkout clkin pm1 reset iap ian ibp ibn icp icn vn vcp vbp vap 2 23 3 4 7 8 9 12 13 14 18 19 22 39 38 37 36 35 34 33 32 29 17 28 27 ade7880 24 26 5 avdd vdd dvdd 6 25 dgnd agnd 0.22f 4.7f 0.1f 4.7f 20pf + + + 3.3v 20pf 16.384mhz same as vcp same as vcp same as iap, ian same as iap, ian 10nf 1k ? 1k ? 1k ? 10k ? 10k ? 1.5k ? 1k ? 10nf 3.3v 3.3 v 1f 10nf 10nf ss/hsa irq1 irq0 10193-007 figure 32. test circuit
data sheet ade7880 rev. a | page 19 of 104 terminology measurement error the error associated with the energy measurement made by the ade7880 is defined by measurement error = %100 7880 ? energytrue energytrue adeby registered energy (1) phase error between channels the high-pass filter (hpf) and digital integrator introduce a slight phase mismatch between the current and the voltage channel. the all digital design ensures that the phase matching between the current channels and voltage channels in all three phases is within 0.1 over a range of 45 hz to 65 hz and 0.2 over a range of 40 hz to 1 khz. this internal phase mismatch can be combined with the external phase error (from current sensor or component tolerance) and calibrated with the phase calibration registers. power supply rejection (psr) this quantifies the ade7880 measurement error as a percen- tage of reading when the power supplies are varied. for the ac psr measurement, a reading at nominal supplies (3.3 v) is taken. a second reading is obtained with the same input signal levels when an ac signal (120 mv rms at 100 hz) is introduced onto the supplies. any error introduced by this ac signal is expressed as a percentage of readingsee the measurement error definition. for the dc psr measurement, a reading at nominal supplies (3.3 v) is taken. a second reading is obtained with the same input signal levels when the power supplies are varied 10%. any error introduced is expressed as a percentage of the reading. adc offset error this refers to the dc offset associated with the analog inputs to the adcs. it means that with the analog inputs connected to agnd, the adcs still see a dc analog input signal. the magni- tude of the offset depends on the gain and input range selection (see the typical performance characteristics section). however, the hpf removes the offset from the current and voltage channels and the power calculation remains unaffected by this offset. gain error the gain error in the adcs of the ade7880 is defined as the difference between the measured adc output code (minus the offset) and the ideal output code (see the current channel adc section and the voltage channel adc section). the difference is expressed as a percentage of the ideal code. cf jitter the period of pulses at one of the cf1, cf2, or cf3 pins is continuously measured. the maximum, minimum, and average values of four consecutive pulses are computed as follows: maximum = max ( period 0 , period 1 , period 2 , period 3 ) minimum = min ( period 0 , period 1 , period 2 , period 3 ) average = 4 3 2 1 0 period period period period + + + the cf jitter is then computed as %100 ? = average minimum maximum cf jitter (2) harmonic power measurement error to measure the error in the harmonic active and reactive power calculations made by the ade7880 , the voltage channel is supplied with a signal comprising a fundamental and one harmonic component with amplitudes equal to 250 mv. the current channel is supplied with a signal comprising a fundamental with amplitude of 50 mv and one harmonic component of the same index as the one in the voltage channel. the amplitude of the harmonic is varied from 250 mv, down to 250 v, 2000 times lower than full scale. the error is defined by measurement error = %100 7880 ? powertrue powertrue adeby registered power (3)
ade7880 data sheet rev. a | page 20 of 104 power management the ade7880 has four modes of operation, determined by the state of the pm0 and pm1 pins (see table 8 ). these pins provide complete control of the ade7880 operation and can easily be connected to an external microprocessor i/o. the pm0 and pm1 pins have internal pull-up resistors. see tabl e 10 and table 1 1 for a list of actions that are recommended before and after setting a new power mode. table 8. power supply modes power supply modes pm1 pm0 psm0, normal power mode 0 1 psm1, reduced power mode 0 0 psm2, low power mode 1 0 psm3, sleep mode 1 1 psm0normal power mode (all parts) in psm0 mode, the ade7880 is fully functional. the pm0 pin is set to high, and the pm1 pin is set to low for the ade7880 to enter this mode. if the ade7880 is in psm1, psm2, or psm3 mode and is switched into psm0 mode, then all control registers take the default values with the exception of the threshold register, lpoilvl, which is used in psm2 mode, and the config2 register, both of which maintain their values. the ade7880 signals the end of the transition period by triggering the irq1 interrupt pin low and setting bit 15 (rstdone) in the status1 register to 1. this bit is 0 during the transition period and becomes 1 when the transition is finished. the status bit is cleared and the irq1 pin is set back to high by writing to the status1 register with the corresponding bit set to 1. bit 15 (rstdone) in the interrupt mask register does not have any functionality attached even if the irq1 pin goes low when bit 15 (rstdone) in the status1 register is set to 1. this makes the rstdone interrupt unmaskable. psm1reduced power mode in the reduced power mode, psm1, the ade7880 measures the mean absolute values (mav) of the 3-phase currents and stores the results in the aimav, bimav, and cimav 20-bit registers. this mode is useful in missing neutral cases in which the voltage supply of the ade7880 is provided by an external battery. the serial ports, i 2 c or spi, are enabled in this mode; the active port can be used to read the aimav, bimav, and cimav registers. it is not recommended to read any of the other registers because their values are not guaranteed in this mode. similarly, a write operation is not taken into account by the ade7880 in this mode. in summary, in this mode, it is not recommended to access any r e g i s t e r o t h e r t h a n a i m av, b i m av, a n d c i m av. t h e c i r c u i t that computes the rms estimates is also active during psm0; therefore, its calibration can be completed in either psm0 mode or in psm1 mode. note that the ade7880 does not provide any register to store or process the corrections resulting from the calibration process. the external microprocessor stores the gain values in connection with these measurements and uses them during psm1 (see the current mean absolute value calculation section for more details on the ximav registers). the 20-bit mean absolute value measurements done in psm1, although available also in psm0, are different from the rms measurements of phase currents and voltages executed only in psm0 and stored in the hxirms and hxvrms 24-bit registers. see the current mean absolute value calculation section for details. if the ade7880 is set in psm1 mode after it was in the psm0 mode, the ade7880 immediately begins the mean absolute value calculations without any delay. the ximav registers are accessible at any time; however, if the ade7880 is set in psm1 mode after it was in psm2 or psm3 modes, the ade7880 signals the start of the mean absolute value computations by triggering the irq1 pin low. the ximav registers can be accessed only after this moment. psm2low power mode in the low power mode, psm2, the ade7880 compares all phase currents against a threshold for a period of 0.02 (lpline[4:0] + 1) seconds, independent of the line frequency. lpline[4:0] are bits[7:3] of the lpoilvl register (see tabl e 9 ). table 9. lpoilvl register bit mnemonic default description [2:0] lpoil[2:0] 111 threshold is put at a value corresponding to full scale multiplied by lpoil/8 [7:3] lpline[4:0] 00000 the measurement period is (lpline[4:0] + 1)/50 sec the threshold is derived from bits[2:0] (lpoil[2:0]) of the lpoilvl register as lpoil[2:0]/8 of full scale. every time one phase current becomes greater than the threshold, a counter is incremented. if every phase counter remains below lpline[4:0] + 1 at the end of the measurement period, then the irq0 pin is triggered low. if a single phase counter becomes greater or equal to lpline[4:0] + 1 at the end of the measurement period, the irq1 pin is triggered low. illustrates how the behaves in psm2 mode when lpline[4:0] = 2 and lpoil[2:0] = 3. the test period is three 50 hz cycles (60 ms), and the phase a current rises above the lpoil[2:0] threshold three times. at the end of the test period, the figure 33 ade7880 irq1 pin is triggered low.
data sheet ade7880 rev. a | page 21 of 104 phase counter = 1 phase counter = 2 phase counter = 3 lpline[4:0] = 2 irq1 ia current lpoil[2:0] threshold 10193-008 figure 33. psm2 mode triggering irq pin for lpline[4:0] = 2 (50 hz systems) the i 2 c or spi port is not functional during this mode. the psm2 mode reduces the power consumption required to monitor the currents when there is no voltage input and the voltage supply of the ade7880 is provided by an external battery. if the irq0 pin is triggered low at the end of a measurement period, this signifies all phase currents stayed below threshold and, therefore, there is no current flowing through the system. at this point, the external microprocessor sets the into sleep mode psm3. if the ade7880 irq1 pin is triggered low at the end of the measurement period, this signifies that at least one current input is above the defined threshold and current is flowing through the system, although no voltage is present at the pins. this situation is often called missing neutral and is considered a tampering situation, at which point the external microprocessor sets the into psm1 mode, measures the mean absolute values of phase currents, and integrates the energy based on their values and the nominal voltage. ade7880 ade7880 it is recommended to use the ade7880 in psm2 mode when bits[2:0] (pga1[2:0]) of the gain register are equal to 1 or 2. these bits represent the gain in the current channel datapath. it is not recommended to use the ade7880 in psm2 mode when the pga1[2:0] bits are equal to 4, 8, or 16. psm3sleep mode (all parts) in sleep mode, the ade7880 has most of its internal circuits turned off and the current consumption is at its lowest level. the i 2 c, hsdc, and spi ports are not functional during this mode, and the reset , sclk/scl, mosi/sda, and ss /hsa pins should be set high. table 10. power modes and related characteristics power mode all registers 1 lpoilvl, config2 i 2 c/spi functionality psm0 state after hardware reset set to default set to default i 2 c enabled all circuits are active and dsp is in idle mode. state after software reset set to default unchanged active serial port is unchanged if lock- in procedure has been previously executed all circuits are active and dsp is in idle mode. psm1 not available psm0 values retained enabled current mean absolute values are computed and the results are stored in the aimav, bimav, and cimav registers. the i 2 c or spi serial port is enabled with limited functionality. psm2 not available psm0 values retained disabled compares phase currents against the threshold set in lpoilvl. triggers irq0 or irq1 pins accordingly. the serial ports are not available. psm3 not available psm0 values retained disabled internal circuits shut down and the serial ports are not available. 1 setting for all registers except the lpoilvl and config2 registers.
ade7880 data sheet rev. a | page 22 of 104 table 11. recommended actions when changing power modes next power mode initial power mode before setting next power mode psm0 psm1 psm2 psm3 stop dsp by setting the run register = 0x0000 current mean absolute values (mav) computed immediately disable hsdc by clearing bit 6 (hsdcen) to 0 in the config register ximav registers can be accessed immediately mask interrupts by setting mask0 = 0x0 and mask1 = 0x0 psm0 erase interrupt status flags in the status0 and status1 registers wait until the irq0 or irq1 pin is triggered accordingly no action necessary wait until the irq1 pin is triggered low psm1 no action necessary poll the status1 register until bit 15 (rstdone) is set to 1 wait until the irq0 or irq1 pin is triggered accordingly no action necessary wait until the irq1 pin is triggered low wait until the irq1 pin triggered low poll the status1 register until bit 15 (rstdone) is set to 1 current mean absolute values compute at this moment psm2 no action necessary ximav registers may be accessed from this moment no action necessary wait until the irq1 pin is triggered low wait until the irq1 pin is triggered low poll the status1 register until bit 15 (rstdone) is set to 1 current mav circuit begins computations at this time psm3 no action necessary ximav registers can be accessed from this moment wait until the irq0 or irq1 pin is triggered accordingly
data sheet ade7880 rev. a | page 23 of 104 power-up procedure por timer turned on ade7880 powered up ade7880 enter psm3 microprocessor sets ade7880 in psm0 microprocessor makes the choice between i 2 c and spi rstdone interrupt triggered 40ms 26ms 0v 3.3v ? 10% 2.0v 10% ade7880 psm0 ready 10193-009 figure 34. power-up procedure the ade7880 contains an on-chip power supply monitor that supervises the power supply (vdd). at power-up, until vdd reaches 2 v 10%, the chip is in an inactive state. as vdd crosses this threshold, the power supply monitor keeps the chip in this inactive state for an additional 26 ms, allowing vdd to achieve 3.3 v ? 10%, the minimum recommended supply voltage. because the pm0 and pm1 pins have internal pull-up resistors and the external microprocessor keeps them high, the ade7880 always powers up in sleep mode (psm3). then, an external circuit (that is, a microprocessor) sets the pm1 pin to a low level, allowing the ade7880 to enter normal mode (psm0). the passage from psm3 mode, in which most of the internal circuitry is turned off, to psm0 mode, in which all functionality is enabled, is accomplished in less than 40 ms (see figure 34 for details). if psm0 mode is the only desired power mode, the pm1 pin may be set low permanently, using a direct connection to ground. the pm0 pin may be left open because the internal pull up resistor ensures its state is high. at power up, the ade7880 briefly passes through psm3 mode and then enters psm0. when the ade7880 enters psm0 mode, the i 2 c port is the active serial port. if the spi port is used, then the ss /hsa pin must be toggled three times, high to low. this action selects the spi port for further use. if i 2 c is the active serial port, bit 1 (i2c_lock) of the config2 register must be set to 1 to lock it in. from this moment, the ignores spurious toggling of the ade7880 ss /hsa pin, and an eventual switch to use the spi port is no longer possible. likewise, if spi is the active serial port, any write to the config2 register locks the port, at which time a switch to use the i 2 c port is no longer possible. only a power- down or by setting the reset pin low can the be reset to use the i 2 c port. once locked, the serial port choice is maintained when the changes psmx power modes. ade7880 ade7880 immediately after entering psm0, the ade7880 sets all registers to their default values, including the config2 and lpoilvl registers. the ade7880 signals the end of the transition period by triggering the irq1 interrupt pin low and setting bit 15 (rstdone) in the status1 register to 1. this bit is 0 during the transition period and becomes 1 when the transition ends. the status bit is cleared and the irq1 pin is returned high by writing the status1 register with the corresponding bit set to 1. because the rstdone is an unmaskable interrupt, bit 15 (rstdone) in the status1 register must be cancelled for the irq1 pin to return high. it is recommended to wait until the irq1 pin goes low before accessing the status1 register to test the state of the rstdone bit. at this point, as a good programming practice, it is also recommended to cancel all other status flags in the status1 and status0 registers by writing the corresponding bits with 1. initially, the dsp is in idle mode, which means it does not execute any instruction. this is the moment to initialize all ade7880 registers. the last register in the queue must be written three times to ensure the register has been initialized. then write 0x0001 into the run register to start the dsp (see the digital signal processor section for details on the run register). if the supply voltage, vdd, drops lower than 2 v 10%, the ade7880 enters an inactive state, which means that no measurements or computations are executed.
ade7880 data sheet rev. a | page 24 of 104 hardware reset the ade7880 has a reset pin. if the is in psm0 mode and the ade7880 reset pin is set low, then the enters the hardware reset state. the must be in psm0 mode for a hardware reset to be considered. setting the ade7880 ade7880 reset pin low while the is in psm1, psm2, and psm3 modes does not have any effect. ade7880 if the ade7880 is in psm0 mode and the reset pin is toggled from high to low and then back to high after at least 10 s, all the registers are set to their default values, including the config2 and lpoilvl registers. the signals the end of the transition period by triggering the ade7880 irq1 interrupt pin low and setting bit 15 (rstdone) in the status1 register to 1. this bit is 0 during the transition period and becomes 1 when the transition ends. the status bit is cleared and the irq1 pin is returned high by writing to the status1 register with the corresponding bit set to 1. after a hardware reset, the dsp is in idle mode, which means it does not execute any instruction. because the i 2 c port is the default serial port of the ade7880 , it becomes active after a reset state. if spi is the port used by the external microprocessor, the procedure to enable it must be repeated immediately after the reset pin is toggled back to high (see the section for details). serial interfaces at this point, it is recommended to initialize all of the ade7880 registers and then write 0x0001 into the run register to start the dsp. see the digital signal processor section for details on the run register. software reset functionality bit 7 (swrst) in the config register manages the software reset functionality in psm0 mode. the default value of this bit is 0. if this bit is set to 1, then the ade7880 enters the software reset state. in this state, almost all internal registers are set to their default values. in addition, the choice of which serial port, i 2 c or spi, is in use remains unchanged if the lock-in procedure has been executed previously (see the serial interfaces section for details). the registers that maintain their values despite the swrst bit being set to 1 are the config2 and lpoilvl registers. when the software reset ends, bit 7 (swrst) in the config register is cleared to 0, the irq1 interrupt pin is set low, and bit 15 (rstdone) in the status1 register is set to 1. this bit is 0 during the transition period and becomes 1 when the transition ends. the status bit is cleared and the irq1 pin is set back high by writing to the status1 register with the corresponding bit set to 1. after a software reset ends, the dsp is in idle mode, which means it does not execute any instruction. as a good programming practice, it is recommended to initialize all the ade7880 registers and then write 0x0001 into the run register to start the dsp (see the digital signal processor section for details on the run register). software reset functionality is not available in psm1, psm2, or psm3 mode.
data sheet ade7880 rev. a | page 25 of 104 theory of operation analog inputs the ade7880 has seven analog inputs forming current and voltage channels. the current channels consist of four pairs of fully differential voltage inputs: iap and ian, ibp and ibn, icp and icn, and inp and inn. these voltage input pairs have a maximum differential signal of 0.5 v. the maximum signal level on analog inputs for the ixp/ixn pair is also 0.5 v with respect to agnd. the maximum common-mode signal allowed on the inputs is 25 mv. figure 35 presents a schematic of the input for the current channels and their relation to the maximum common-mode voltage. iap, ibp, icp, or inp ian, ibn, icn, or inn v cm v 2 v 1 +500m v v cm v 1 + v 2 differential input v 1 + v 2 = 500mv max peak common mode v cm = 25mv max ?500mv 10193-010 figure 35. maximum input level, current channels, gain = 1 all inputs have a programmable gain amplifier (pga) with a possible gain selection of 1, 2, 4, 8, or 16. the gain of ia, ib, and ic inputs is set in bits[2:0] (pga1[2:0]) of the gain register. the gain of the in input is set in bits[5:3] (pga2[2:0]) of the gain register; thus, a different gain from the ia, ib, or ic inputs is possible. see table 43 for details on the gain register. the voltage channel has three single-ended voltage inputs: vap, vbp, and vcp. these single-ended voltage inputs have a maximum input voltage of 0.5 v with respect to vn. the maximum signal level on analog inputs for vxp and vn is also 0.5 v with respect to agnd. the maximum common-mode signal allowed on the inputs is 25 mv. figure 36 presents a schematic of the voltage channels inputs and their relation to the maximum common-mode voltage. k v in gain selection ixn, vn ixp, vyp v in notes 1. x = a, b, c, n y = a, b, c. 10193-012 figure 36. maximum input level, voltage channels, gain = 1 all inputs have a programmable gain with a possible gain selection of 1, 2, 4, 8, or 16. to set the gain, use bits[8:6] (pga3[2:0]) in the gain register (see table 43 ). figure 37 shows how the gain selection from the gain register works in both current and voltage channels. vap, vbp, or vcp vn v cm v 1 + 500mv v cm v 1 differential input v 1 + v 2 = 500mv max peak common mode v cm = 25mv max ? 500m v 10193-011 figure 37. pga in current and voltage channels analog-to-digital conversion the ade7880 has seven sigma-delta (-) analog-to-digital converters (adcs). in psm0 mode, all adcs are active. in psm1 mode, only the adcs that measure the phase a, phase b, and phase c currents are active. the adcs that measure the neutral current and the a, b, and c phase voltages are turned off. in psm2 and psm3 modes, the adcs are powered down to minimize power consumption. for simplicity, the block diagram in figure 38 shows a first- order - adc. the converter is composed of the - modulator and the digital low-pass filter. 24 r c + ? clkin/16 digital low-pass filter integrator v ref 1-bit dac latched comparator analog low-pass filter .....10100101..... + ? 10193-013 figure 38. first-order -? adc a - modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. in the ade7880 , the sampling clock is equal to 1.024 mhz (clkin/16). the 1-bit dac in the feedback loop is driven by the serial data stream. the dac output is subtracted from the input signal. if the loop gain is high enough, the average value of the dac output (and, therefore, the bit stream) can approach that of the input signal level. for any given input value in a single sampling interval, the data from the 1-bit adc is virtually meaningless. only when a large number of samples are averaged is a meaningful result obtained. this averaging is carried out in the second part of the adc, the digital low-pass filter. by averaging a large number of bits from the modulator, the low-pass filter can produce 24-bit data-words that are proportional to the input signal level.
ade7880 data sheet rev. a | page 26 of 104 the - converter uses two techniques to achieve high resolu- tion from what is essentially a 1-bit conversion technique. the first is oversampling. oversampling means that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. for example, the sampling rate in the ade7880 is 1.024 mhz, and the bandwidth of interest is 40 hz to 3.3 khz. oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. with the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered, as shown in figure 39 . however, oversampling alone is not efficient enough to improve the signal-to-noise ratio (snr) in the band of interest. for example, an oversampling factor of 4 is required just to increase the snr by a mere 6 db (1 bit). to keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. in the - modulator, the noise is shaped by the integrator, which has a high-pass-type response for the quantization noise. this is the second technique used to achieve high resolution. the result is that most of the noise is at the higher frequencies where it can be removed by the digital low-pass filter. this noise shaping is shown in figure 39 . noise signal noise signal 03.34 512 frequency (khz) high resolution output from digital lpf 1024 03.34 512 frequency (khz) 1024 digital filter shaped noise antialias filte r (rc) sampling frequency 10193-014 figure 39. noise reduction due to oversampling and noise shaping in the analog modulator antialiasing filter figure 38 also shows an analog low-pass filter (rc) on the input to the adc. this filter is placed outside the ade7880 , and its role is to prevent aliasing. aliasing is an artifact of all sampled systems as shown in figure 40 . aliasing means that frequency components in the input signal to the adc, which are higher than half the sampling rate of the adc, appear in the sampled signal at a frequency below half the sampling rate. frequency components above half the sampling frequency (also known as the nyquist frequency, that is, 512 khz) are imaged or folded back down below 512 khz. this happens with all adcs regardless of the architecture. in the example shown, only frequencies near the sampling frequency, that is, 1.024 mhz, move into the band of interest for metering, that is, 40 hz to 3.3 khz. to attenuate the high frequency (near 1.024 mhz) noise and prevent the distortion of the band of interest, a low-pass filter (lpf) must be introduced. for conventional current sensors, it is recommended to use one rc filter with a corner frequency of 5 khz for the attenuation to be sufficiently high at the sampling frequency of 1.024 mhz. the 20 db per decade attenuation of this filter is usually sufficient to eliminate the effects of aliasing for conventional current sensors. however, for a di/dt sensor such as a rogowski coil, the sensor has a 20 db per de cade gain. this neutralizes the 20 db per decade attenuation produced by the lpf. therefore, when using a di/dt sensor, take care to offset the 20 db per decade gain. one simple approach is to cascade one additional rc filter, thereby producing a ?40 db per decade attenuation. a liasing effects sampling frequency image frequencies 0 3.3 4 512 frequency (khz) 1024 10193-015 figure 40. aliasing effects adc transfer function all adcs in the ade7880 are designed to produce the same 24-bit signed output code for the same input signal level. with a full-scale input signal of 0.5 v and an internal reference of 1.2 v, the adc output code is nominally 5,326,737 (0x514791) and usually varies for each ade7880 around this value. the code from the adc can vary between 0x800000 (?8,388,608) and 0x7fffff (+8,388,607); this is equivalent to an input signal level of 0.787 v. however, for specified performance, do not exceed the nominal range of 0.5 v; adc performance is guaranteed only for input signals lower than 0.5 v. current channel adc figure 41 shows the adc and signal processing path for input ia of the current channels (it is the same for ib and ic). the adc outputs are signed twos complement 24-bit data-words and are available at a rate of 8 ksps (thousand samples per second). with the specified full-scale analog input signal of 0.5v, the adc produces its maximum output code value. figure 41 shows a full-scale voltage signal applied to the differ- ential inputs (iap and ian). the adc output swings between ?5,326,737 (0xaeb86f) and +5,326,737 (0x514791). note that these are nominal values and every ade7880 varies around these values. the input, in, corresponds to the neutral current of a 3-phase system. if no neutral line is present, connect this input to agnd. the datapath of the neutral current is similar to the path of the phase currents as shown in figure 42 .
data sheet ade7880 rev. a | page 27 of 104 aigain[23:0] dsp reference hpfen bit config3[0] digital integrator inten bit config[0] total/fundamental active and reactive power calculation current peak, overcurrent detect iawv waveform sample register current rms (irms) calculation hpf adc pga1 iap zx detection pga1 bits gain[2:0] 1, 2, 4, 8, 16 v in v in ian analog input range analog output range 0x514791 = +5,326,737 zx signal data range 0v 0xaeb86f = ?5,326,737 0x5a7540 = +5,928,256 current channel data range after integration 0v 0xa58ac0 = ?5,928,256 0x514791 = +5,326,737 current channel data range 0v 0xaeb86f = ?5,326,737 +0.5v/gain ?0.5v/gain 0v lpf1 10193-016 figure 41. current channel signal path nigain[23:0] dsp reference hpfen bit config3[0] digital integrator ininten bit config3[3] inwv waveform sample register current rms (irms) calculation hpf adc pga2 iap pga2 bits gain[5:3] 1, 2, 4, 8, 16 v in ian 10193-017 figure 42. neutral current signal path current waveform gain registers there is a multiplier in the signal path of each phase and neutral current. the current waveform can be changed by 100% by writing a corresponding twos complement number to the 24-bit signed current waveform gain registers (aigain, bigain, cigain, and nigain). for example, if 0x400000 is written to those registers, the adc output is scaled up by 50%. to scale the input by ?50%, write 0xc00000 to the registers. equation 4 describes mathematically the function of the current waveform gain registers. current waveform = ? ? ? ? ? ? ? ? + 23 2 1 register gain currentofcontent outputadc (4) changing the content of the aigain, bigain, cigain, or ingain registers affects all calculations based on its current; that is, it affects the corresponding phase active/reactive/ apparent energy and current rms calculation. in addition, waveform samples scale accordingly. note that the serial ports of the ade7880 work on 32-, 16-, or 8-bit words, and the dsp works on 28 bits. the 24-bit aigain, bigain, cigain, and nigain registers are accessed as 32-bit registers with the four most significant bits (msbs) padded with 0s and sign extended to 28 bits. see figure 43 for details. 31 28 27 24 23 0 24-bit number 0000 bits[27:24] are equal to bit 23 bit 23 is a sign bit 10193-018 figure 43. 24-bit xigain transmitted as 32-bit words current channel hpf the adc outputs can contain a dc offset. this offset can create errors in power and rms calculations. high-pass filters (hpfs) are placed in the signal path of the phase and neutral currents and of the phase voltages. if enabled, the hpf eliminates any dc offset on the current channel. all filters are implemented in the dsp and, by default, they are all enabled: bit 0 (hpfen) of the config3[7:0] register is set to 1. all filters are disabled by setting bit 0 (hpfen) to 0.
ade7880 data sheet rev. a | page 28 of 104 current channel sampling the waveform samples of the current channel are taken at the output of hpf and stored in the 24-bit signed registers, iawv, ibwv, icwv, and inwv at a rate of 8 ksps. all power and rms calculations remain uninterrupted during this process. bit 17 (dready) in the status0 register is set when the iawv, ibwv, icwv, and inwv registers are available to be read using the i 2 c or spi serial port. setting bit 17 (dready) in the mask0 register enables an interrupt to be set when the dready flag is set. see the digital signal processor section for more details on bit dready. as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words. when the iawv, ibwv, icwv, and inwv 24-bit signed registers are read from the ade7880 , they are transmitted sign extended to 32 bits. see figure 44 for details. 31 24 23 22 0 24-bit signed number bits[31:24] are equal to bit 23 bit 23 is a sign bit 10193-019 figure 44. 24-bit ixwv register transmitted as 32-bit signed word the ade7880 contains a high speed data capture (hsdc) port that is specially designed to provide fast access to the waveform sample registers. see the hsdc interface section for more details. di/dt current sensor and digital integrator the di/dt sensor detects changes in the magnetic field caused by the ac current. figure 45 shows the principle of a di/dt current sensor. magnetic field created by current (directly proportional to current) + emf (electromotive force) ? induced by changes in magnetic flux density (di/dt) 10193-020 figure 45. principle of a di/dt current sensor the flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. the changes in the magnetic flux density passing through a conductor loop generate an electromotive force (emf) between the two ends of the loop. the emf is a voltage signal that is propor- tional to the di/dt of the current. the voltage output from the di/dt current sensor is determined by the mutual inductance between the current carrying conductor and the di/dt sensor. due to the di/dt sensor, the current signal needs to be filtered before it can be used for power measurement. on each phase and neutral current datapath, there are built-in digital integrators to recover the current signal from the di/dt sensor. the digital integrators placed on the phase currents data paths are independent of the digital integrator placed in the neutral current data path. this allows for using a different current sensor to measure the neutral current (for example a current transformer) from the current sensors used to measure the phase currents (for example di/dt sensors). the digital integrators are managed by bit 0 (inten) of the config register and by bit 3 (ininten) of the config3 register. bit 0 (inten) of the config register manages the integrators in the phase current channels. bit 3 (ininten) of the config3 register manages the integrator in the neutral current channel. when the inten bit is 0 (default), all integrators in the phase current channels are disabled. when inten bit is 1, the integrators in the phase currents datapaths are enabled. when the ininten bit is 0 (default), the integrator in the neutral current channel is disabled. when the ininten bit is 1, the integrator in the neutral current channel is enabled. figure 46 and figure 47 show the magnitude and phase response of the digital integrator. note that the integrator has a ?20 db/dec attenuation and approximately ?90 phase shift. when combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. however, the di/dt sensor has a 20 db/dec gain associated with it and generates sig- nificant high frequency noise. at least a second order antialiasing filter is needed to avoid noise aliasing back in the band of interest when the adc is sampling (see the antialiasing filter section). 50 0 ?50 ?100 ?50 0 magnitude (db) phase (degrees) 0 500 1000 1500 2000 2500 3000 3500 4000 frequency (hz) 0.01 0.1 1 10 100 1000 frequency (hz) 10193-021 figure 46. combined gain and phase response of the digital integrator the dicoeff 24-bit signed register is used in the digital integrator algorithm. at power-up or after a reset, its value is 0x000000. before turning on the integrator, this register must be initialized with 0xfff8000. dicoeff is not used when the integrator is turned off and can remain at 0x000000 in that case.
data sheet ade7880 rev. a | page 29 of 104 ?30 ? 15 ?20 ?25 ?89.96 ?89.97 ?89.98 ?89.99 magnitude (db) phase (degrees) 30 35 40 45 50 55 60 65 70 frequency (hz) 30 35 40 45 50 55 60 65 70 frequency (hz) 10193-022 figure 47. combined gain and phase response of the digital integrator (40 hz to 70 hz) as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words. similar to the registers shown in figure 43 , the dicoeff 24-bit signed register is accessed as a 32-bit register with four msbs padded with 0s and sign extended to 28 bits, which practically means it is transmitted equal to 0x0fff8000. when the digital integrator is switched off, the ade7880 can be used directly with a conventional current sensor, such as a current transformer (ct). voltage channel adc figure 48 shows the adc and signal processing chain for input va in the voltage channel. the vb and vc channels have similar processing chains. the adc outputs are signed twos complement 24-bit words and are available at a rate of 8 ksps. with the specified full-scale analog input signal of 0.5 v, the adc produces its maximum output code value. figure 48 shows a full-scale voltage signal being applied to the differential inputs (va and vn). the adc output swings between ?5,326,737 (0xaeb86f) and +5,326,737 (0x514791). note these are nominal values and every ade7880 varies around these values. avgain[23:0] reference hpfen bit config3[0] dsp total/fundamental active and reactive power calculation v oltage peak, overvoltage, sag detect vawv waveform sample register current rms (vrms) calculation hpf adc pga3 vap zx detection pga3 bits gain[8:6] 1, 2, 4, 8, 16 v in v in vn analog input range analog output range 0x514791 = +5,326,737 zx signal data range 0v 0xaeb86f = ?5,326,737 0x514791 = +5,326,737 voltage channel data range 0v 0xaeb86f = ?5,326,737 +0.5v/gain ?0.5v/gain 0v lpf1 10193-023 figure 48. voltage channel datapath
ade7880 data sheet rev. a | page 30 of 104 voltage waveform gain registers there is a multiplier in the signal path of each phase voltage. the voltage waveform can be changed by 100% by writing a corresponding twos complement number to the 24-bit signed voltage waveform gain registers (avgain, bvgain, and cvgain). for example, if 0x400000 is written to those registers, the adc output is scaled up by 50%. to scale the input by ?50%, write 0xc00000 to the registers. equation 5 describes mathe- matically the function of the current waveform gain registers. voltage waveform = ? ? ? ? ? ? ? ? + 23 2 1 register gainvoltageofcontent output adc (5) changing the content of the avgain, bvgain, and cvgain registers affects all calculations based on its voltage; that is, it affects the corresponding phase active/reactive/apparent energy and voltage rms calculation. in addition, waveform samples are scaled accordingly. as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words, and the dsp works on 28 bits. as presented in figure 43 , the avgain, bvgain, and cvgain registers are accessed as 32-bit registers with four msbs padded with 0s and sign extended to 28 bits. voltage channel hpf as explained in the current channel hpf section, the adc outputs can contain a dc offset that can create errors in power and rms calculations. hpfs are placed in the signal path of the phase voltages, similar to the ones in the current channels. bit 0 (hpfen) of config3 register can enable or disable the filters. see the current channel hpf section for more details. voltage channel sampling the waveform samples of the voltage channel are taken at the output of hpf and stored into vawv, vbwv, and vcwv 24- bit signed registers at a rate of 8 ksps. all power and rms calculations remain uninterrupted during this process. bit 17 (dready) in the status0 register is set when the vawv, vbwv, and vcwv registers are available to be read using the i 2 c or spi serial port. setting bit 17 (dready) in the mask0 register enables an interrupt to be set when the dready flag is set. see the digital signal processor section for more details on bit dready. as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words. similar to registers presented in figure 44 , the vawv, vbwv, and vcwv 24-bit signed registers are transmitted sign extended to 32 bits. the ade7880 contains an hsdc port especially designed to provide fast access to the waveform sample registers. see the hsdc interface section for more details. changing phase voltage data path the ade7880 can direct one phase voltage input to the computational data path of another phase. for example, phase a voltage can be introduced in the phase b computational data path, which means all powers computed by the ade7880 in phase b are based on phase a voltage and phase b current. bits[9:8] (vtoia[1:0]) of the config register manage the phase a voltage measured at the vap pin. if vtoia[1:0] = 00 (default value), the voltage is directed to the phase a computa- tional data path. if vtoia[1:0] = 01, the voltage is directed to the phase b path. if vtoia[1:0] = 10, the voltage is directed to the phase c path. if vtoia[1:0] = 11, the ade7880 behaves as if vtoia[1:0] = 00. bits[11:10] (vtoib[1:0]) of the config register manage the phase b voltage measured at the vbp pin. if vtoib[1:0] = 00 (default value), the voltage is directed to the phase b computa- tional data path. if vtoib[1:0] = 01, the voltage is directed to the phase c path. if vtoib[1:0] = 10, the voltage is directed to the phase a path. if vtoib[1:0] = 11, the ade7880 behaves as if vtoib[1:0] = 00. bits[13:12] (vtoic[1:0]) of the config register manage the phase c voltage measured at the vcp pin. if vtoic[1:0] = 00 (default value), the voltage is directed to phase c computational data path, if vtoic[1:0] = 01, the voltage is directed to the phase a path. if vtoic[1:0] = 10, the voltage is directed to the phase b path. if vtoic[1:0] = 11, the ade7880 behaves as if vtoic[1:0] = 00. i a va ib vb ic vc phase a computational datapath phase b computational datapath phase c computational datapath vtoia[1:0] = 01, phase a voltage directed to phase b vtoib[1:0] = 01, phase b voltage directed to phase c vtoic[1:0] = 01, phase c voltage directed to phase a cphcal bphcal aphcal 10193-024 figure 49. phase voltages used in different datapaths figure 49 presents the case in which the phase a voltage is used in the phase b data path, the phase b voltage is used in the phase c data path, and the phase c voltage is used in the phase a data path.
data sheet ade7880 rev. a | page 31 of 104 power quality measurements zero-crossing detection the ade7880 has a zero-crossing (zx) detection circuit on the phase current and voltage channels. the neutral current data path does not contain a zero-crossing detection circuit. zero- crossing events are used as a time base for various power quality measurements and in the calibration process. the output of lpf1 is used to generate zero crossing events. the low-pass filter is intended to eliminate all harmonics of 50 hz and 60 hz systems, and to help identify the zero-crossing events on the fundamental components of both current and voltage channels. the digital filter has a pole at 80 hz and is clocked at 256 khz. as a result, there is a phase lag between the analog input signal (one of ia, ib, ic, va, vb, and vc) and the output of lpf1. the error in zx detection is 0.0703 for 50 hz systems (0.0843 for 60 hz systems). the phase lag response of lpf1 results in a time delay of approximately 31.4 or 1.74 ms (at 50 hz) between its input and output. the overall delay between the zero crossing on the analog inputs and zx detection obtained after lpf1 is about 39.6 or 2.2 ms (at 50 hz). the adc and hpf introduce the additional delay. the lpf1 cannot be disabled to assure a good resolution of the zx detection. figure 50 shows how the zero-crossing signal is detected. gain[23:0] reference hpfen bit config3[0] dsp hpf pga adc ia, ib, ic, or v a, vb, vc zx detection lpf1 ia, ib, ic, in or va, vb, vc 39.6 or 2.2ms @ 50hz 1 0.855 0v zx zx zx zx lpf1 output 10193-025 figure 50. zero-crossing detection on voltage and current channels to provide further protection from noise, input signals to the voltage channel with amplitude lower than 10% of full scale do not generate zero-crossing events at all. the current channel zx detection circuit is active for all input signals independent of their amplitudes. the ade7880 contains six zero-crossing detection circuits, one for each phase voltage and current channel. each circuit drives one flag in the status1 register. if a circuit placed in the phase a voltage channel detects one zero-crossing event, bit 9 (zxva) in the status1 register is set to 1. similarly, the phase b voltage circuit drives bit 10 (zxvb), the phase c voltage circuit drives bit 11 (zxvc), and circuits placed in the current channel drive bit 12 (zxia), bit 13 (zxib), and bit 14 (zxic) in the status1 register. if a zx detection bit is set in the mask1 register, the irq1 interrupt pin is driven low and the corresponding status flag is set to 1. the status bit is cleared and the irq1 pin is set to high by writing to the status1 register with the status bit set to 1. zero-crossing timeout every zero-crossing detection circuit has an associated timeout register. this register is loaded with the value written into the 16-bit zxtout register and is decremented (1 lsb) every 62.5 s (16 khz clock). the register is reset to the zxtout value every time a zero crossing is detected. the default value of this register is 0xffff. if the timeout register decrements to 0 before a zero crossing is detected, one of bits[8:3] of the status1 register is set to 1. bit 3 (zxtova), bit 4 (zxtovb), and bit 5 (zxtovc) in the status1 register refer to phase a, phase b, and phase c of the voltage channel; bit 6 (zxtoia), bit 7 (zxtoib), and bit 8 (zxtoic) in the status1 register refer to phase a, phase b, and phase c of the current channel. if a zxtoix or zxtovx bit is set in the mask1 register, the irq1 interrupt pin is driven low when the corresponding status bit is set to 1. the status bit is cleared and the irq1 pin is returned to high by writing to the status1 register with the status bit set to 1. the resolution of the zxout register is 62.5 s (16 khz clock) per lsb. thus, the maximum timeout period for an interrupt is 4.096 sec: 2 16 /16 khz. figure 51 shows the mechanism of the zero-crossing timeout detection when the voltage or the current signal stays at a fixed dc level for more than 62.5 s zxtout s. 16-bit internal register value zxtout voltage or current signal irq1 interrupt pin zxzoxy flag in s tatus1[31:0], x = v, a y = a, b, c 0v 10193-026 figure 51. zero-crossing timeout detection phase sequence detection the ade7880 has on-chip phase sequence error detection circuits. this detection works on phase voltages and considers only the zero crossings determined by their negative-to-positive transitions. the regular succession of these zero-crossing events is phase a followed by phase b followed by phase c (see figure 53 ). if the sequence of zero-crossing events is, instead, phase a followed by phase c followed by phase b, then bit 19 (seqerr) in the status1 register is set.
ade7880 data sheet rev. a | page 32 of 104 if bit 19 (seqerr) in the mask1 register is set to 1 and a phase sequence error event is triggered, the irq1 interrupt pin is driven low. the status bit is cleared and the irq1 pin is set high by writing to the status1 register with the status bit 19 (seqerr) set to 1. the phase sequence error detection circuit is functional only when the ade7880 is connected in a 3-phase, 4-wire, three voltage sensors configuration (bits[5:4], consel[1:0] in the accmode register, set to 00). in all other configurations, only two voltage sensors are used; therefore, it is not recommended to use the detection circuit. in these cases, use the time intervals between phase voltages to analyze the phase sequence (see the time interval between phases section for details). figure 52 presents the case in which phase a voltage is not followed by phase b voltage but by phase c voltage. every time a negative-to-positive zero crossing occurs, bit 19 (seqerr) in the status1 register is set to 1 because such zero crossings on phase c, phase b, or phase a cannot come after zero crossings from phase a, phase c, or respectively, phase b zero crossings. zx b zx c phase c phase b phase a a, b, c phase voltages after lpf1 bit 19 (seqerr) in s tatus1 register irq1 zx a status1[19] set to 1 status1[19] cancelled by a write to the status1 register with seqerr bit set 10193-027 figure 52. seqerr bit set to 1 when phase a voltage is followed by phase c voltage once a phase sequence error has been detected, the time measurement between various phase voltages (see the time interval between phases section) can help to identify which phase voltage should be considered with another phase current in the computational data path. bits[9:8] (vtoia[1:0]), bits[11:10] (vtoib[1:0]), and bits[13:12] (vtoic[1:0]) in the config register can be used to direct one phase voltage to the data path of another phase. see the changing phase voltage data path section for details. time interval between phases the ade7880 has the capability to measure the time delay between phase voltages, between phase currents, or between voltages and currents of the same phase. the negative-to-positive transitions identified by the zero-crossing detection circuit are used as start and stop measuring points. only one set of such measurements is available at one time, based on bits[10:9] (anglesel[1:0]) in the compmode register. zx c zx b phase b phase c phase a zx a 10193-028 figure 53. regular succession of phase a, phase b, and phase c when the anglesel[1:0] bits are set to 00, the default value, the delays between voltages and currents on the same phase are measured. the delay between phase a voltage and phase a current is stored in the 16-bit unsigned angle0 register (see figure 54 for details). in a similar way, the delays between voltages and currents on phase b and phase c are stored in the angle1 and angle2 registers, respectively. phase a current angle0 phase a voltage 10193-029 figure 54. delay between phase a voltage and phase a current is stored in the angle0 register when the anglesel[1:0] bits are set to 01, the delays between phase voltages are measured. the delay between phase a voltage and phase c voltage is stored into the angle0 register. the delay between phase b voltage and phase c voltage is stored in the angle1 register, and the delay between phase a voltage and phase b voltage is stored in the angle2 register (see figure 55 for details). when the anglesel[1:0] bits are set to 10, the delays between phase currents are measured. similar to delays between phase voltages, the delay between phase a and phase c currents is stored into the angle0 register, the delay between phase b and phase c currents is stored in the angle1 register, and the delay between phase a and phase b currents is stored into the angle2 register (see figure 55 for details). phase b phase c phase a angle2 angle0 angle1 10193-030 figure 55. delays between ph ase voltages (currents) the angle0, angle1, and angle2 registers are 16-bit unsigned registers with 1 lsb corresponding to 3.90625 s (256 khz clock), which means a resolution of 0.0703 (360 50 hz/256 khz) for 50 hz systems and 0.0843 (360 60 hz/
data sheet ade7880 rev. a | page 33 of 104 256 khz) for 60 hz systems. the delays between phase voltages or phase currents are used to characterize how balanced the load is. the delays between phase voltages and currents are used to compute the power factor on each phase as shown in the following equation 6: cos x = cos ? ? ? ? ? ? khz256 360 line f anglex o (6) where f line = 50 hz or 60 hz. period measurement the ade7880 provides the period measurement of the line in the voltage channel. the period of each phase voltage is measured and stored in three different registers, aperiod, bperiod, and cperiod. the period registers are 16-bit unsigned registers and update every line period. because of the lpf1 filter (see figure 50 ), a settling time of 30 ms to 40 ms is associated with this filter before the measurement is stable. the period measurement has a resolution of 3.90625 s/lsb (256 khz clock), which represents 0.0195% (50 hz/256 khz) when the line frequency is 50 hz and 0.0234% (60 hz/256 khz) when the line frequency is 60 hz. the value of the period registers for 50 hz networks is approximately 5120 (256 khz/50 hz) and for 60 hz networks is approximately 4267 (256 khz/60 hz). the length of the registers enables the measurement of line frequencies as low as 3.9 hz (256 khz/2 16 ). the period registers are stable at 1 lsb when the line is established and the measurement does not change. the following equations can be used to compute the line period and frequency using the period registers: [] sec 3e256 :0] period[15 t l = (7) ]hz[ 3e256 :0] period[15 f l = (8) phase voltage sag detection the ade7880 can be programmed to detect when the absolute value of any phase voltage drops below or grows above a certain peak value for a number of half-line cycles. the phase where this event takes place and the state of the phase voltage relative to the threshold is identified in bits[14:12] (vsphase[x]) of the phstatus register. an associated interrupt is triggered when any phase drops below or grows above a threshold. this condition is illustrated in figure 56 . figure 56 shows phase a voltage falling below a threshold that is set in the sag level register (saglvl) for four half-line cycles (sagcyc = 4). when bit 16 (sag) in the status1 register is set to 1 to indicate the condition, bit vsphase[0] in the phstatus register is also set to 1 because the phase a voltage is below saglvl. the microcontroller then writes back status1 register with bit 16 (sag) set to 1 to erase the bit and bring irq1 interrupt pin back high. then the phase a voltage stays above the saglvl threshold for four half-line cycles (sagcyc = 4). the bit 16 (sag) in status1 register is set to 1 to indicate the condition and the bit vsphase[0] in the phstatus register is set back to 0. bits vsphase[1] and vsphase[2] relate to the sag events on phase b and phase c in the same way: when phase b or phase c voltage stays below saglvl, they are set to 1. when the phase voltages are above saglvl, they are set to 0. phase a voltage bit 16 (sag) in status1[31:0] vsphase[0] = phstatus[12] full scale saglvl[23:0] sagcyc[7:0] = 0x4 phase b voltage vsphase[1] = phstatus[13] irq1 pin status1[16] cancelled by a write to status1[31:0] with sag bit set phstatus[12] set to 1 because phase a voltage was below saglvl for sagcyc half line cycles phstatus[12] cleared to 0 because phase a voltage was above saglvl for sagcyc half line cycles status[16] set to 1 phstatus[13] set to 1 irq1 pin goes high because status1[16] cancelled by a write to status[31:0] with sag bit set sagcyc[7:0] = 0x4 10193-031 figure 56. sag detection the sagcyc register represents the number of half-line cycles the phase voltage must remain below or above the level indicated in the saglvl register to trigger a sag interrupt ; 0 is not a valid number for sagcyc. for example, when the sag cycle (sagcyc[7:0]) contains 0x07, the sag flag in the status1 register is set at the end of the seventh half line cycle for which the line voltage falls below the threshold. if bit 16 (sag) in mask1 is set, the irq1 interrupt pin is driven low in case of a sag event in the same moment the status bit 16 (sag) in status1 register is set to 1. the sag status bit in the status1 register and the irq1 pin is returned to high by writing to the status1 register with the status bit set to 1. when the phase b voltage falls below the indicated threshold into the saglvl register for two line cycles, bit vsphase[1] in the phstatus register is set to 1 (see figure 56 ). simultane- ously, bit 16 (sag) in the status1 register is set to 1 to indicate the condition. note that the internal zero-crossing counter is always active. by setting the saglvl register, the first sag detection result is, therefore, not executed across a full sagcyc period. writing to the sagcyc register when the saglvl register is already initia- lized resets the zero-crossing counter, thus ensuring that the first sag detection result is obtained across a full sagcyc period.
ade7880 data sheet rev. a | page 34 of 104 th e recommended procedure to manage sag events is the following: 1. enable sag interrupts in the mask1 register by setting bit 16 (sag) to 1. 2. when a sag event happens, the irq1 interrupt pin goes low and bit 16 (sag) in the status1 is set to 1. 3. the status1 register is read with bit 16 (sag) set to 1. 4. the phstatus register is read, identifying on which phase or phases a sag event happened. 5. the status1 register is written with bit 16 (sag) set to 1. immediately, the sag bit is erased. sag level set the content of the saglvl[23:0] sag level register is compared to the absolute value of the output from hpf. writing 5,928,256 (0x5a7540) to the saglvl register, puts the sag detection level at full scale (see the volt age c hannel ad c section), thus; the sag event is triggered continuously. writing 0x00 or 0x01 puts the sag detection level at 0, therefore, the sag event is never triggered. 0000 0000 24-bit number 31 24 23 0 10193-03 2 figure 57. saglvl register transmitted as a 32-bit word as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words. the saglvl register is accessed as a 32-bit register with eight msbs padded with 0s. see figure 57 for details. peak detection the ade7880 records the maximum absolute values reached by the voltage and current channels over a certain number of half- line cycles and stores them into the less significant 24 bits of the vpeak and ipeak 32-bit registers. the peakcyc register contains the number of half-line cycles used as a time base for the measurement. the circuit uses the zero-crossing points identified by the zero-crossing detection circuit. bits[4:2] (peaksel[2:0]) in the mmode register select the phases upon which the peak measurement is performed. bit 2 selects phase a, bit 3 selects phase b, and bit 4 selects phase c. selecting more than one phase to monitor the peak values decreases proportionally the measurement period indicated in the peakcyc register because zero crossings from more phases are involved in the process. when a new peak value is determined, one of bits[26:24] (ipphase[2:0] or vpphase[2:0]) in the ipeak and vpeak registers is set to 1, identifying the phase that triggered the peak detection event. for example, if a peak value has been identified on phase a current, bit 24 (ipphase[0]) in the ipeak register is set to 1. if next time a new peak value is measured on phase b, bit 24 (ipphase[0]) of the ipeak register is cleared to 0, and bit 25 (ipphase[1]) of the ipeak register is set to 1. figure 58 shows the composition of the ipeak and vpeak registers. peak detected on phase c 00000 31 27 26 25 24 23 0 24-bit unsigned number peak detected on phase a ipphase/vpphase bits peak detected on phase b 10193-033 figure 58. composition of ipeak[31:0] and vpeak[31:0] registers phase a c urrent phase b c urrent bit 24 of ipeak bit 25 of ipeak peak value written into ipeak at the end of first peakcyc period end of first peakcyc = 16 period bit 24 of ipeak cleared to 0 at the end of second peakcyc period bit 25 of ipeak set to 1 at the end of second peakcyc period end of second peakcyc = 16 period peak value written into ipeak at the end of second peakcyc period 10193-034 figure 59. peak level detection figure 59 shows how the ade7880 records the peak value on the current channel when measurements on phase a and phase b are enabled (bit peaksel[2:0] in the mmode register are 011). peakcyc is set to 16, meaning that the peak measurement cycle is four line periods. the maximum absolute value of phase a is the greatest during the first four line periods (peakcyc = 16), so the maximum absolute value is written into the less signifi- cant 24 bits of the ipeak register, and bit 24 (ipphase[0]) of the ipeak register is set to 1 at the end of the period. this bit remains at 1 for the duration of the second peakcyc period of four line cycles. the maximum absolute value of phase b is the greatest during the second peakcyc period; therefore, the maximum absolute value is written into the less significant 24 bits of the ipeak register, and bit 25 (ipphase[1]) in the ipeak register is set to 1 at the end of the period. at the end of the peak detection period in the current channel, bit 23 (pki) in the status1 register is set to 1. if bit 23 (pki) in the mask1 register is set, the irq1 interrupt pin is driven low at the end of the peakcyc period, and status bit 23 (pki) in the status1 register is set to 1. in a similar way, at the end of the peak detection period in the voltage channel, bit 24 (pkv) in the status1 register is set to 1. if bit 24 (pkv) in the mask1 register is set, the irq1 interrupt pin is driven low at the end of peakcyc period and status bit 24 (pkv) in the status1
data sheet ade7880 rev. a | page 35 of 104 register is set to 1. to find the phase that triggered the interrupt, one of either the ipeak or vpeak registers is read immediately after reading the status1 register. next, the status bits are cleared, and the irq1 pin is set to high by writing to the status1 register with the status bit set to 1. note that the internal zero-crossing counter is always active. by setting bits[4:2] (peaksel[2:0]) in the mmode register, the first peak detection result is, therefore, not executed across a full peakcyc period. writing to the peakcyc register when the peaksel[2:0] bits are set resets the zero-crossing counter, thereby ensuring that the first peak detection result is obtained across a full peakcyc period. overvoltage and overcurrent detection the ade7880 detects when the instantaneous absolute value measured on the voltage and current channels becomes greater than the thresholds set in the ovlvl and oilvl 24-bit unsigned registers. if bit 18 (ov) in the mask1 register is set, the irq1 interrupt pin is driven low in case of an overvoltage event. there are two status flags set when the irq1 interrupt pin is driven low: bit 18 (ov) in the status1 register and one of bits[11:9] (ovphase[2:0]) in the phstatus register to identify the phase that generated the overvoltage. the status bit 18 (ov) in the status1 register and all bits[11:9] (ovphase[2:0]) in the phstatus register are cleared, and the irq1 pin is set to high by writing to the status1 register with the status bit set to 1. presents overvoltage detection in the phase a voltage. figure 60 ovlvl[23:0] bit 18 (ov) of status1 bit 9 (ovphase) of phstatus phase a voltage channel overvoltage detected status1[18] and phstatus[9] cancelled by a write of status1 with ov bit set. 10193-035 figure 60. overvoltage detection whenever the absolute instantaneous value of the voltage goes above the threshold from the ovlvl register, bit 18 (ov) in the status1 register and bit 9 (ovphase[0]) in the phstatus register are set to 1. bit 18 (ov) of the status1 register and bit 9 (ovphase[0]) in the phstatus register are cancelled when the status1 register is written with bit 18 (ov) set to 1. th e recommended procedure to manage overvoltage events is the following: 1. enable ov interrupts in the mask1 register by setting bit 18 (ov) to 1. 2. when an overvoltage event happens, the irq1 interrupt pin goes low. 3. the status1 register is read with bit 18 (ov) set to 1. 4. the phstatus register is read, identifying on which phase or phases an overvoltage event happened. 5. the status1 register is written with bit 18 (ov) set to 1. in this moment, bit ov is erased and also all bits[11:9] (ovphase[2:0]) of the phstatus register. in case of an overcurrent event, if bit 17 (oi) in the mask1 register is set, the irq1 interrupt pin is driven low. immediately, bit 17 (oi) in the status1 register and one of bits[5:3] (oiphase[2:0]) in the phstatus register, which identify the phase that generated the interrupt, are set. to find the phase that triggered the interrupt, the phstatus register is read immediately after reading the status1 register. next, status bit 17 (oi) in the status1 register and bits[5:3] (oiphase[2:0]) in the phstatus register are cleared and the irq1 pin is set to high by writing to the status1 register with the status bit set to 1. the process is similar with overvoltage detection. overvoltage and overcurrent level set the content of the overvoltage (ovlvl), and overcurrent, (oilvl) 24-bit unsigned registers is compared to the absolute value of the voltage and current channels. the maximum value of these registers is the maximum value of the hpf outputs: +5,326,737 (0x514791). when the ovlvl or oilvl register is equal to this value, the overvoltage or overcurrent conditions are never detected. writing 0x0 to these registers signifies the overvoltage or overcurrent conditions are continuously detected, and the corresponding interrupts are permanently triggered. as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words. similar to the register presented in figure 57 , oilvl and ovlvl registers are accessed as 32-bit registers with the eight msbs padded with 0s.
ade7880 data sheet rev. a | page 36 of 104 neutral current mismatch in 3-phase systems, the neutral current is equal to the algebraic sum of the phase currents i n ( t ) = i a ( t ) + i b ( t ) + i c ( t ) if there is a mismatch between these two quantities, then a tamper situation may have occurred in the system. the ade7880 computes the sum of the phase currents adding the content of the iawv, ibwv, and icwv registers, and storing the result into the isum 28-bit signed register: i sum (t) = i a (t) + i b (t) + i c (t). isum is computed every 125 s (8 khz frequency), the rate at which the current samples are available, and bit 17 (dready) in the status0 register is used to signal when the isum register can be read. see the digital signal processor section for more details on bit dready. to re cover i sum (t) value from the isum register, use the following equation: fs m ax sum i adc isum[27:0] ti = )( where: adc max = 5,928,256, the adc output when the input is at full scale. i fs is the full-scale adc phase current. note that the ade7880 also computes the rms of isum and stores it into nirms register when bit 2 (insel) in config3 register is set to 1 (see current rms calculation section for details). the ade7880 computes the difference between the absolute values of isum and the neutral current from the inwv register, take its absolute value and compare it against the isumlvl threshold. if isumlvl inwv isum ? , then it is assumed that the neutral current is equal to the sum of the phase currents, and the system functions correctly. if isumlvl inwv isum >? , then a tamper situation may have occurred, and bit 20 (mismtch) in the status1 register is set to 1. an interrupt attached to the flag can be enabled by setting bit 20 (mismtch) in the mask1 register. if enabled, the irq1 pin is set low when status bit mismtch is set to 1. the status bit is cleared and the irq1 pin is set back to high by writing to the status1 register with bit 20 (mismtch) set to 1. if isumlvl inwv isum ? , then mismtch = 0 if isumlvl inwv isum >? , then mismtch = 1 isumlvl, the positive threshold used in the process, is a 24-bit signed register. because it is used in a comparison with an absolute value, always set isumlvl as a positive number, somewhere between 0x00000 and 0x7fffff. isumlvl uses the same scale of the current adcs outputs, so writing +5,326,737 (0x514791) to the isumlvl register puts the mismatch detection level at full scale; see the current channel adc section for details. writing 0x000000, the default value, or a negative value, signifies the mismtch event is always triggered. the right value for the application should be written into the isumlvl register after power-up or after a hardware/software reset to avoid continuously triggering mismtch events. as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words and the dsp works on 28 bits. as presented in figure 61 , isum, the 28-bit signed register, is accessed as a 32-bit register with the four most significant bits padded with 0s. 31 28 27 bit 27 is a sign bit 0 28-bit signed number 0000 10193-036 figure 61. the isum[27:0] register is transmitted as a 32-bit word similar to the registers presented in figure 43 , the isumlvl register is accessed as a 32-bit register with four most significant bits padded with 0s and sign extended to 28 bits. phase compensation as described in the current channel adc and voltage channel adc sections, the data path for both current and voltages is the same. the phase error between current and voltage signals introduced by the ade7880 is negligible. however, the ade7880 must work with transducers that may have inherent phase errors. for example, a current transformer (ct) with a phase error of 0.1 to 3 is not uncommon. these phase errors can vary from part to part, and they must be corrected to perform accurate power calculations. the errors associated with phase mismatch are particularly noticeable at low power factors. the ade7880 provides a means of digitally calibrating these small phase errors. the ade7880 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for the small phase errors. the phase calibration registers (aphcal, bphcal, and cphcal) are 10-bit registers that can vary the time advance in the voltage channel signal path from ?374.0 s to +61.5 s. negative values written to the phcal registers represent a time advance whereas positive values represent a time delay. one lsb is equivalent to 0.976 s of time delay or time advance (clock rate of 1.024 mhz). with a line frequency of 60 hz, this gives a phase resolution of 0.0211 (360 60 hz/1.024 mhz) at the fundamental. this corresponds to a total correction range of ?8.079 to +1.329 at 60 hz. at 50 hz, the correction range is
data sheet ade7880 rev. a | page 37 of 104 figure 63 illustrates how the phase compensation is used to remove x = ?1 phase lead in ia of the current channel from the external current transducer (equivalent of 55.5 s for 50 hz systems). to cancel the lead (1) in the current channel of phase a, a phase lead must be introduced into the corresponding voltage channel. using equation 8, aphcal is 57 least significant bits, rounded up from 56.8. the phase lead is achieved by introducing a time delay of 55.73 s into the phase a current. ?6.732 to +1.107 and the resolution is 0.0176 (360 50 hz/ 1.024 mhz). given a phase error of x degrees, measured using the phase voltage as the reference, the corresponding lsbs are computed dividing x by the phase resolution (0.0211/lsb for 60 hz and 0.0176/lsb for 50 hz). results between ?383 and +63 only are acceptable; numbers outside this range are not accepted. if the current leads the voltage, the result is negative and the absolute value is written into the phcal registers. if the current lags the voltage, the result is positive and 512 is added to the result before writing it into xphcal. aphcal , bphcal , or cphcal = ? ? ? ? ? ? ? ? ? ? ? ? ? ? >+ 0,512 _ 0, _ x resolution phase x x resolution phase x (9) as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words. as shown in figure 62 , aphcal, bphcal, and cphcal 10-bit registers are accessed as 16-bit registers with the six msbs padded with 0s. 0000 00 15 10 9 0 xphcal 10193-03 7 figure 62. xphcal registers communicated as 16-bit registers phase calibration aphcal = 57 adc pga3 vap va vn adc pga1 iap ia ian phase compensation achi eved delaying ia by 56s 50hz 1 va ia va ia 10193-038 figure 63. phase calibration on voltage channels
ade7880 data sheet rev. a | page 38 of 104 reference circuit the nominal reference voltage at the ref in/out pin is 1.2 0.075% v. this is the reference voltage used for the adcs in the ade7880 . the ref in/out pin can be overdriven by an external source, for example, an external 1.2 v reference. the voltage of the ade7880 reference drifts slightly with temperature; see the specifications section for the temperature coefficient specification (in ppm/c). the value of the temperature drift varies from part to part. because the reference is used for all adcs, any x percentage drift in the reference results in a 2 percentage deviation of the meter accuracy. the reference drift resulting from temperature changes is usually very small and typically much smaller than the drift of other components on a meter. alternatively, the meter can be calibrated at multiple temperatures. if bit 0 (extrefen) in the config2 register is cleared to 0 (the default value), the ade7880 uses the internal voltage reference. if the bit is set to 1, the external voltage reference is used. set the config2 register during the psm0 mode. its value is maintained during the psm1, psm2, and psm3 power modes. digital signal processor the ade7880 contains a fixed function digital signal processor (dsp) that computes all powers and rms values. it contains program memory rom and data memory ram. the program used for the power and rms computations is stored in the program memory rom and the processor executes it every 8 khz. the end of the computations is signaled by setting bit 17 (dready) to 1 in the status0 register. an interrupt attached to this flag can be enabled by setting bit 17 (dready) in the mask0 register. if enabled, the irq0 pin is set low and status bit dready is set to 1 at the end of the computations. the status bit is cleared and the irq0 pin is set to high by writing to the status0 register with bit 17 (dready) set to 1. the registers used by the dsp are located in the data memory ram, at addresses between 0x4380 and 0x43be. the width of this memory is 28 bits. a two-stage pipeline is used when write operations to the data memory ram are executed. this means two things: when only one register needs to be initialized, write it two more times to ensure the value has been written into ram. when two or more registers need to be initialized, write the last register in the queue two more times to ensure the value has been written into ram. as explained in the power-up procedure section, at power-up or after a hardware or software reset, the dsp is in idle mode. no instruction is executed. all the registers located in the data memory ram are initialized at 0, their default values and they can be read/written without any restriction. the run register, used to start and stop the dsp, is cleared to 0x0000. the run register needs to be written with 0x0001 for the dsp to start code execution. it is recommended to first initialize all ade7880 registers located in the data memory ram with their desired values. next, write the last register in the queue two additional times to flush the pipeline and then write the run register with 0x0001. in this way, the dsp starts the computations from a desired configuration. to protect the integrity of the data stored in the data memory ram of the dsp (between address 0x4380 and address 0x43be), a write protection mechanism is available. by default, the protection is disabled and registers placed between 0x4380 and 0x43be can be written without restriction. when the protection is enabled, no writes to these registers is allowed. registers can be always read, without restriction, independent of the write protection state. to enable the protection, write 0xad to an internal 8-bit register located at address 0xe7fe, followed by a write of 0x80 to an internal 8-bit register located at address 0xe7e3. to disable the protection, write 0xad to an internal 8-bit register located at address 0xe7fe, followed by a write of 0x00 to an internal 8-bit register located at address 0xe7e3. it is recommended to enable the write protection before starting the dsp. if any data memory ram based register needs to be changed, simply disable the protection, change the value and then enable back the protection. there is no need to stop the dsp in order to change these registers. th e recommended procedure to initialize the registers located in the data memory ram is: ? initialize all registers. write the last register in the queue three times to ensure its value was written into the ram. all the other registers of the ade7880 should also be initialized here. ? enable the write protection by writing 0xad to an internal 8-bit register located at address 0xe7fe, followed by a write of 0x80 to an internal 8-bit register located at address 0xe7e3. ? read back all data memory ram registers to ensure they were initialized with the desired values. ? in the remote case one or more registers are not initialized correctly, disable the protection by writing 0xad to an internal 8-bit register located at address 0xe7fe, followed by a write of 0x00 to an internal 8-bit register located at address 0xe7e3. initialize again the registers. write the last register in the queue three times. enable the write protection by writing 0xad to an internal 8-bit register located at address 0xe7fe, followed by a write of 0x80 to an internal 8-bit register located at address 0xe7e3. ? start the dsp by setting run = 1. th ere is no obvious reason to stop the dsp if the ade7880 is maintained in psm0 normal mode. all ade7880 registers, including ones located in the data memory ram, can be modified without stopping the dsp. however, to stop the dsp, 0x0000 has to be written into run register. to restart the dsp, one of the following procedures must be followed:
data sheet ade7880 rev. a | page 39 of 104 ? if the ade7880 registers located in the data memory ram have not been modified, write 0x0001 into the run register to start the dsp. ? if the ade7880 registers located in the data memory ram have to be modified, first execute a software or a hardware reset, initialize all ade7880 registers at desired values, enable the write protection and then write 0x0001 into the run register to start the dsp. as mentioned in the power management section, when the ade7880 switch out of psm0 power mode, it is recommended to stop the dsp by writing 0x0000 into the run register (see table 1 0 and table 11 for the recommended actions when changing power modes). root mean square measurement root mean square (rms) is a measurement of the magnitude of an ac signal. its definition can be both practical and mathematical. defined practically, the rms value assigned to an ac signal is the amount of dc required to produce an equivalent amount of power in the load. mathematically, the rms value of a conti- nuous signal f(t) is defined as () dttf t rmsf = t 0 2 1 (10) for time sampling signals, rms calculation involves squaring the signal, taking the average, and obtaining the square root. [] = = n n nf n rmsf 1 2 1 (11) equation 10 implies that for signals containing harmonics, the rms calculation contains the contribution of all harmonics, not only the fundamental. the ade7880 uses two different methods to calculate rms values. the first one is very accurate and is active only in psm0 mode. the second one is less accurate, uses the estimation of the mean absolute value (mav) measurement, is active in psm0 and psm1 modes. the ade7880 also computes the rms values of various fundamental and harmonic components of phase currents, phase voltages and neutral current as part of the harmonic calculations block. refer to harmonics calculations section for details. the first method is to low-pass filter the square of the input signal (lpf) and take the square root of the result (see figure 65 ). if ( k k k tkftf + = = sin2)( 1 ) ) (12) then, () ( ? = = = +?+?+ ++ ?= mk mk m k m k k k k k k tm tkff tkfftf 1, 1 2 1 2 2 sin sin 22 )22cos( )( (13) after the lpf and the execution of the square root, the rms value of f(t) is obtained by = = 1 2 k k ff (14) the rms calculation based on this method is simultaneously processed on all seven analog input channels. each result is available in the 24-bit registers: airms, birms, cirms, avrms, bvrms, cvrms, and nirms. the second method computes the absolute value of the input signal and then filters it to extract its dc component. it computes the absolute mean value of the input. if the input signal in equation 12 has a fundamental component only, its average value is ? ? ? ? ? ? ? ? ? ? ?= t t 1 t 1 dc dttfdttf t f 2 2 0 )sin(2)sin(2 1 1 dc f f = 2 2 the calculation based on this method is simultaneously processed only on the three phase currents. each result is available in the 20-bit registers aimav, bmav, and cmav. note that the proportionality between mav and rms values is maintained for the fundamental components only. if harmonics are present in the current channel, the mean absolute value is no longer proportional to rms. current rms calculation this section presents the first approach to compute the rms values of all phase and neutral currents. the ade7880 also computes the rms of the sum of the instantaneous values of the phase currents if bit 2 (insel) in the config3 register is set to 1. note that the instantaneous value of the sum is stored into isum register presented in the neutral current mismatch section. in 3-phase four wired systems that only require sensing the phase currents, this value provides a measure of the neutral current. figure 65 shows the detail of the signal processing chain for the rms calculation on one of the phases of the current channel. the current channel rms value is processed from the samples used in the current channel. the current rms values are signed 24-bit values and they are stored into the airms, birms, cirms, nirms registers. the update rate of the current rms measurement is 8 khz. if bit 2 (insel) of the config3 register is 0 (default), the nirms register contains the rms value of the neutral current. if the insel bit is 1, the nirms register contains the rms value of the sum of the instantaneous values of the phase currents. with the specified full-scale analog input signal of 0.5 v, the adc produces an output code that is approximately 5,326,737. the equivalent rms value of a full-scale sinusoidal signal is 3,766,572 (0x39792c), independent of the line frequency. if
ade7880 data sheet rev. a | page 40 of 104 table 12. settling time for i rms measurement integrator status 50 hz input signals the integrator is enabled, that is, when bit 0 (inten) in the config register is set to 1, the equivalent rms value of a full- scale sinusoidal signal at 50 hz is 3,759,718 (0x395e66) and at 60 hz is 3,133,207 (0x2fcf17). 60 hz input signals integrator off 580 ms 580 ms integrator on 700 ms 700 ms the accuracy of the current rms is typically 0.1% error from the full-scale input down to 1/1000 of the full-scale input when pga = 1. additionally, this measurement has a bandwidth of 3.3 khz. it is recommended to read the rms registers synchronous to the voltage zero crossings to ensure stability. the irq1 inter- rupt can be used to indicate when a zero crossing has occurred (see the section). shows the settling time for the i rms measurement, which is the time it takes for the rms register to reflect the value at the input to the current channel when starting from 0. interrupts table 12 as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words. similar to the register presented in figure 64 , the airms, birms, cirms, nirms 24-bit signed registers are accessed as 32-bit registers with the eight msbs padded with 0s. 31 24 23 0 24-bit number 0000 0000 10193-039 figure 64. 24-bit airms, birms, cirms and nirms registers transmitted as 32-bit words 0xaeb86f = ?5,326,737 0x514791 = 5,326,737 0v current signal from hpf or integrator (if enabled) lpf x 2 2 7 xirmsos[23:0] xirms[23:0] 10193-040 figure 65. current rms signal processing
data sheet ade7880 rev. a | page 41 of 104 current rms offset compensation the ade7880 incorporates a current rms offset compensation register for each phase: airmsos, birmsos, cirmsos, and nirmsos. these are 24-bit signed registers that are used to remove offsets in the current rms calculations. an offset can exist in the rms calculation due to input noises that are integrated in the dc component of i 2 (t). one lsb of the current rms offset compensation register is equivalent to one lsb of the current rms register. assuming that the maximum value from the current rms calculation is 3,766,572 with full-scale ac inputs (50 hz), one lsb of the current rms offset represents 0.00045% 10013767/1283767 2 ? ? ? ? ? ? ? + of the rms measurement at 60 db down from full scale. conduct offset calibration at low current; avoid using currents equal to zero for this purpose. irmsos rmsirmsi += 128 2 0 (15) where i rms 0 is the rms measurement without offset correction. as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words and the dsp works on 28 bits. similar to the register presented in figure 43 , the airmsos, birmsos, cirmsos, and nirmsos 24-bit signed registers are accessed as 32-bit registers with four msbs padded with 0s and sign extended to 28 bits. current mean absolute value calculation this section presents the second approach to estimate the rms values of all phase currents using the mean absolute value (mav) method. this approach is used in psm1 mode, to allow energy accumulation based on current rms values when the missing neutral case demonstrates to be a tamper attack. this data path is active also in psm0 mode to allow for its gain calibration. the gain is used in the external microprocessor during psm1 mode. the mav value of the neutral current is not computed using this method. figure 66 shows the details of the signal processing chain for the mav calculation on one of the phases of the current channel. current signal c oming from adc ximav[23:0] hpf hpf |x| 10193-041 figure 66. current mav signal processing for psm1 mode the current channel mav value is processed from the samples used in the current channel waveform sampling mode. the samples are passed through a high-pass filter to eliminate the eventual dc offsets introduced by the adcs and the absolute values are computed. the outputs of this block are then filtered to obtain the average. the current mav values are unsigned 20-bit values and they are stored in the aimav, bimav, and cimav registers. the update rate of this mav measurement is 8 khz. 207000 207500 208000 208500 209000 209500 210000 210500 211000 211500 212000 45 50 55 frequency (hz) lsb 60 65 10193-042 figure 67. ximav register values at full scale, 45 hz to 65 hz line frequencies the mav values of full-scale sinusoidal signals of 50 hz and 60 hz are 209,686 and 210,921, respectively. as seen in figure 67 , there is a 1.25% variation between the mav estimate at 45 hz and the one at 65 hz for full-scale sinusoidal inputs. the accuracy of the current mav is typically 0.5% error from the full-scale input down to 1/100 of the full-scale input. additionally, this measurement has a bandwidth of 3.3 khz. the settling time for the current mav measurement, that is the time it takes for the mav register to reflect the value at the input to the current channel within 0.5% error, is 500 ms. as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words. as presented in figure 68 , the aimav, bimav, and cimav 20- bit unsigned registers are accessed as 32-bit registers with the 12 msbs padded with 0s. 31 20 19 0 20-bit unsigned number 0000 0000 0000 10193-043 figure 68. ximav registers transmitted as 32-bit registers current mav gain and offset compensation the current rms values stored in the aimav, bimav, and cimav registers can be calibrated using gain and offset coefficients corresponding to each phase. it is recommended to calculate the gains in psm0 mode by supplying the ade7880 with nominal currents. the offsets can be estimated by supplying the ade7880 with low currents, usually equal to the minimum value at which the accuracy is required. every time the external microcontroller reads the aimav, bimav, and cimav registers, it uses these coefficients stored in its memory to correct them.
ade7880 data sheet rev. a | page 42 of 104 voltage channel rms calculation figure 69 shows the detail of the signal processing chain for the rms calculation on one of the phases of the voltage channel. the voltage channel rms value is processed from the samples used in the voltage channel. the voltage rms values are signed 24-bit values and they are stored into the registers avrms, bvrms, and cvrms. the update rate of the current rms measurement is 8 khz. with the specified full-scale analog input signal of 0.5 v, the adc produces an output code that is approximately 5,326,737. the equivalent rms value of a full-scale sinusoidal signal is 3,766,572 (0x39792c), independent of the line frequency. the accuracy of the voltage rms is typically 0.1% error from the full-scale input down to 1/1000 of the full-scale input. additionally, this measurement has a bandwidth of 3.3 khz. it is recommended to read the rms registers synchronous to the voltage zero crossings to ensure stability. the irq1 interrupt can be used to indicate when a zero crossing has occurred (see the section). interrupts the v rms measurement settling time is 580 ms for both 50 hz and 60 hz input signals. the v rms measurement settling time is the time it takes for the rms register to reflect the value at the input to the voltage channel when starting from 0. as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words. similar to the register presented in figure 57 , the avrms, bvrms, and cvrms 24-bit signed registers are accessed as 32-bit registers with the eight msbs padded with 0s. 0xaeb86f = ?5,326,737 0x14791 = +5,326,737 0v v oltage signal from hpf lpf x 2 2 7 xvrmsos[23:0] xvrms[23:0] 10193-044 figure 69. voltage rms signal processing
data sheet ade7880 rev. a | page 43 of 104 voltage rms offset compensation the ade7880 incorporates voltage rms offset compensation registers for each phase: avrmsos, bvrmsos, and cvrmsos. these are 24-bit signed registers used to remove offsets in the voltage rms calculations. an offset can exist in the rms calcula- tion due to input noises that are integrated in the dc component of v 2 (t). one lsb of the voltage rms offset compensation register is equivalent to one lsb of the voltage rms register. assuming that the maximum value from the voltage rms calculation is 3,766,572 with full-scale ac inputs (50 hz), one lsb of the current rms offset represents 0.00045% ( 10013767/1283767 2 ? ? ? ? ? ? ? + of the rms measurement at 60 db down from full scale. conduct offset calibration at low current; avoid using voltages equal to zero for this purpose. vrmsos rmsvrmsv += 128 2 0 (16) where v rms 0 is the rms measurement without offset correction. as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words and the dsp works on 28 bits. similar to registers presented in figure 43 , the avrmsos, bvrmsos, and cvrmsos 24-bit registers are accessed as 32-bit registers with the four most significant bits padded with 0s and sign extended to 28 bits. voltage rms in 3-phase three wire delta configurations in 3-phase three wire delta configurations, phase b is considered the ground of the system, and phase a and phase c voltages are measured relative to it. this configuration is chosen using consel bits equal to 01 in accmode register (see table 15 for all configurations where the ade7880 may be used). in this situation, all phase b active, reactive, and apparent powers are 0. in this configuration, the ade7880 computes the rms value of the line voltage between phase a and phase c and stores the result into bvrms register. bvgain and bvrmsos registers may be used to calibrate bvrms register computed in this configuration. active power calculation the ade7880 computes the total active power on every phase. total active power considers in its calculation all fundamental and harmonic components of the voltages and currents. in addition, the ade7880 computes the fundamental active power, the power determined only by the fundamental components of the voltages and currents. the ade7880 also computes the harmonic active powers, the active powers determined by the harmonic components of the voltages and currents. see the harmonics calculations section for details. total active power calculation electrical power is defined as the rate of energy flow from source to load, and it is given by the product of the voltage and current waveforms. the resulting waveform is called the instantaneous power signal, and it is equal to the rate of energy flow at every instant of time. the unit of power is the watt or joules/sec. if an ac system is supplied by a voltage, v(t), and consumes the current, i(t), and each of them contains harmonics, then sin2)( 1 = = k k vtv ( kt + k ) (17) () k k k tkiti + = = sin2)( 1 where: v k , i k are rms voltage and current, respectively, of each harmonic. k , k are the phase delays of each harmonic. the instantaneous power in an ac system is p ( t ) = v ( t) i ( t ) = cos( k C k ) ? cos(2kt + k + k ) + {cos[( k ? m ) t + k C m ] C cos[( k + m ) t + k + m ]} = 1 k kk iv = 1 k kk iv = mk mk m k iv 1, (18) the average power over an integral number of line cycles (n) is given by the equation in equation 19. p = () = = 1 0 1 k kk nt ivdttp nt cos( k C k ) (19) where: t is the line cycle period. p is referred to as the total active or total real power. note that the total active power is equal to the dc component of the instantaneous power signal p ( t ) in equation 18, that is, = 1 k kk iv cos( k C k ) this is the equation used to calculate the total active power in the ade7880 for each phase. the equation of fundamental active power is obtained from equation 18 with k = 1, as follows: fp = v 1 i 1 cos( 1 C 1 ) (20) figure 70 shows how the ade7880 computes the total active power on each phase. first, it multiplies the current and voltage signals in each phase. next, it extracts the dc component of the instantaneous power signal in each phase (a, b, and c) using lpf2, the low-pass filter. if the phase currents and voltages contain only the fundamental component, are in phase (that is 1 = 1 = 0), and they correspond to full-scale adc inputs, then multiplying them results in an instantaneous power signal that has a dc component, v 1 i 1 , and a sinusoidal component, v 1 i 1 cos(2t); figure 71 shows the corresponding waveforms.
ade7880 data sheet rev. a | page 44 of 104 instantaneous phase a active power hpfen bit config3[0] hpf digital signal processor aigain avgain hpfen bit config3[0] inten bit config[0] lpsel bit config3[1] hpf va ia lpf apgain awattos aphcal 2 4 awatt : 10193-045 figure 70. total active power data path instantaneous power signal instantaneous active power signal: v rms i rms p(t)= v rms i rms ? v rms i rms cos(2 t) 0x339cbbc = 54,119,356 v rms i rms 0x19ce5de = 27,059,678 0x000 0000 i(t) = 2 i rms sin( t) v(t) = 2 v rms sin( t) 10193-046 figure 71. active power calculation because lpf2 does not have an ideal brick wall frequency response, the active power signal has some ripple due to the instantaneous power signal. this ripple is sinusoidal and has a frequency equal to twice the line frequency. because the ripple is sinusoidal in nature, it is removed when the active power signal is integrated over time to calculate the energy. bit 1 (lpfsel) of config3 register selects the lpf2 strength. if lpfsel is 0 (default), the settling time is 650 ms and the ripple attenuation is 65 db. if lpfsel is 1, the settling time is 1300 ms and the ripple attenuation is 128 db. figure 72 shows the frequency response of lpf2 when lpfsel is 0 and figure 73 shows the frequency response of lpf2 when lpfsel is 1. the ade7880 stores the instantaneous total phase active powers into the awatt, bwatt, and cwatt registers. their equation is = = 1 k fs k fs k i i u u xwatt cos( k C k ) pmax 4 2 1 (21) where: u fs , i fs are the rms values of the phase voltage and current when the adc inputs are at full scale. pmax = 27,059,678 it is the instantaneous power computed when the adc inputs are at full scale and in phase. the xwatt[23:0] waveform registers can be accessed using various serial ports. refer to the waveform sampling mode section for more details. 0 ?5 ?10 ?15 ?20 ?25 0.1 13 frequency (hz) magnitude (db) 1 0 10193-172 figure 72. frequency response of the lpf used to filter instantaneous power in each phase when the lpfsel bit of config3 is 0 (default) 0 ?10 ?20 ?30 ?40 0.1 11 frequency (hz) magnitude (db) 0 10193-173 figure 73. frequency response of the lpf used to filter instantaneous power in each phase when the lpfsel bit of config3 is 1
data sheet ade7880 rev. a | page 45 of 104 fundamental active power calculation the ade7880 computes the fundamental active power using a proprietary algorithm that requires some initializations function of the frequency of the network and its nominal voltage measured in the voltage channel. bit 14 (selfreq) in the compmode register must be set according to the frequency of the network in which the ade7880 is connected. if the network frequency is 50 hz, clear this bit to 0 (the default value). if the network fre- quency is 60 hz, set this bit to 1. in addition, initialize the vlevel 24-bit signed register with a positive value based on the following equation: 6 104 = n fs u u vlevel (22) where: u fs is the rms value of the phase voltages when the adc inputs are at full scale. u n is the rms nominal value of the phase voltage. as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words and the dsp works on 28 bits. similar to the registers presented in figure 43 , the vlevel 24-bit signed register is accessed as a 32-bit register with four most significant bits padded with 0s and sign extended to 28 bits. table 13 presents the settling time for the fundamental active power measurement. table 13. settling time for fundamental active power input signals 63% pmax 100% pmax 375 ms 875 ms active power gain calibration note that the average active power result from the lpf2 output in each phase can be scaled by 100% by writing to the phases watt gain 24-bit register (apgain, bpgain, cpgain). the xpgain registers are placed on data paths of all powers computed by the ade7880 : total active powers, fundamental active and reactive powers and apparent powers. this is possible because all power data paths have identical overall gains. therefore, to compensate the gain errors in various powers data paths it is sufficient to analyze only one power data path, for example the total active power, calculate the correspondent apgain, bpgain and cpgain registers and all the power data paths are gain compensated. the power gain registers are twos complement, signed registers and have a resolution of 2 ?23 /lsb. equation 23 describes mathematically the function of the power gain registers. ? ? ? ? ? ? + = 23 2 1 2 gister gainpower output lpf datapower average re (23) the output is scaled by ?50% by writing 0xc00000 to the watt gain registers, and it is increased by +50% by writing 0x400000 to them. these registers are used to calibrate the active, reactive and apparent power (or energy) calculation for each phase. as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words, and the dsp works on 28 bits. similar to registers presented in figure 43 , the apgain, bpgain, and cpgain 24-bit signed registers are accessed as 32-bit registers with the four msbs padded with 0s and sign extended to 28 bits. active power offset calibration the ade7880 incorporates a watt offset 24-bit register on each phase and on each active power. the awattos, bwattos, and cwattos registers compensate the offsets in the total active power calculations, and the afwattos, bfwattos, and cfwattos registers compensate offsets in the fundamental active power calculations. these are signed twos complement, 24-bit registers that are used to remove offsets in the active power calculations. an offset can exist in the power calculation due to crosstalk between channels on the pcb or in the chip itself. one lsb in the active power offset register is equivalent to 1 lsb in the active power multiplier output. with full-scale current and voltage inputs, the lpf2 output is pmax = 27,059,678. at ?80 db down from the full scale (active power scaled down 10 4 times), one lsb of the active power offset register represents 0.0369% of pmax. as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words and the dsp works on 28 bits. similar to registers presented in figure 43 , the awattos, bwattos, cwattos, afwattos, b f wat t o s , a n d c f wat t o s 2 4 - b i t s i g n e d r e g i s t e r s a r e accessed as 32-bit registers with the four msbs padded with 0s and sign extended to 28 bits. sign of active power calculation the average active power is a signed calculation. if the phase difference between the current and voltage waveform is more than 90, the average power becomes negative. negative power indicates that energy is being injected back on the grid. the ade7880 has sign detection circuitry for active power calculations. it can monitor the total active powers or the fundamental active powers. as described in the active energy calculation section, the active energy accumulation is performed in two stages. every time a sign change is detected in the energy accumulation at the end of the first stage, that is, after the energy accumulated into the internal accumulator reaches the wthr register threshold, a dedicated interrupt is triggered. the sign of each phase active power can be read in the phsign register. bit 6 (revapsel) in the accmode register sets the type of active power being monitored. when revapsel is 0, the default value, the total active power is monitored. when revapsel is 1, the fundamental active power is monitored.
ade7880 data sheet rev. a | page 46 of 104 bits[8:6] (revapc, revapb, and revapa, respectively) in the status0 register are set when a sign change occurs in the power selected by bit 6 (revapsel) in the accmode register. bits[2:0] (cwsign, bwsign, and awsign, respectively) in the phsign register are set simultaneously with the revapc, revapb, and revapa bits. they indicate the sign of the power. when they are 0, the corresponding power is positive. when they are 1, the corresponding power is negative. bit revapx of status0 and bit xwsign in the phsign register refer to the total active power of phase x, the power type being selected by bit 6 (revapsel) in the accmode register. interrupts attached to bits[8:6] (revapc, revapb, and revapa, respectively) in the status0 register can be enabled by setting bits[8:6] in the mask0 register. if enabled, the irq0 pin is set low, and the status bit is set to 1 whenever a change of sign occurs. to find the phase that triggered the interrupt, the phsign register is read immediately after reading the status0 register. next, the status bit is cleared and the irq0 pin is returned to high by writing to the status0 register with the corresponding bit set to 1. active energy calculation as previously stated, power is defined as the rate of energy flow. this relationship can be expressed mathematically as d t denergy power = (24) conversely, energy is given as the integral of power, as follows: () dttpenergy = (25) total and fundamental active energy accumulations are always signed operations. negative energy is subtracted from the active energy contents. internal accumulator threshold hpfen bit config3[0] hpf digital signal processor aigain avgain hpfen bit config3[0] inten bit config[0] hpf va ia lpf apgain awattos aphcal 2 4 awatt : wthr 34 27 26 0 0 32-bit register awatthr[31:0] revapa bit in status0[31:0] 10193-049 figure 74. total active energy accumulation
data sheet ade7880 rev. a | page 47 of 104 the ade7880 achieves the integration of the active power signal in two stages (see figure 74 ). the process is identical for both total and fundamental active powers. the first stage accumulates the instantaneous phase total or fundamental active power at 1.024mhz, although they are computed by the dsp at 8 khz rate. every time a threshold is reached, a pulse is generated and the threshold is subtracted from the internal register. the sign of the energy in this moment is considered the sign of the active power (see the sign of active power calculation section for details). the second stage consists of accumulating the pulses generated at the first stage into internal 32-bit accu- mulation registers. the content of these registers is transferred to watt-hour registers, xwatthr and xfwatthr, when these registers are accessed. threshold 1 pulse = 1lsb of watthr[31:0] first stage of active power accumulation pulses generated after first stage 10193-050 figure 75. active power accumulation inside the dsp figure 75 explains this process. the threshold is formed by concatenating the wthr 8-bit unsigned register to 27 bits equal to 0. it is introduced by the user and is common for total and fundamental active powers on all phases. its value depends on how much energy is assigned to one lsb of watt-hour regis- ters. supposing a derivative of wh [10 n wh], n as an integer, is desired as one lsb of the xwatthr register, wthr is computed using the following equation: 27 2 103600 = (26) where: pmax = 27,059,678 = 0x19ce5de as the instantaneous power computed when the adc inputs are at full scale. f s = 1.024 mhz, the frequency at which every instantaneous power computed by the dsp at 8 khz is accumulated. u fs , i fs are the rms values of phase voltages and currents when the adc inputs are at full scale. wthr register is an 8-bit unsigned number, so its maximum value is 2 8 ? 1. its default value is 0x3. values lower than 3, that is 2 or 1 should be avoided and 0 should never be used as the threshold must be a non-zero value. this discrete time accumulation or summation is equivalent to integration in continuous time following the description in equation 27. () () ? ? ? ? ? ? == = 0 0t lim n tntp dttpenergy (27) where: n is the discrete time sample number. t is the sample period. in the ade7880 , the total phase active powers are accumulated in the awatthr, bwatthr, and cwat thr 32-bit signed registers, and the fundamental phase active powers are a c c u m u l a t e d i n a f wat t h r , b f wat t h r , a n d c f wat t h r 32-bit signed registers. the active energy register content can roll over to full-scale negative (0x80000000) and continue increasing in value when the active power is positive. conversely, if the active power is negative, the energy register underflows to full-scale positive (0x7fffffff) and continues decreasing in value. the ade7880 provides a status flag to signal when one of the xwatthr and xfwatthr registers is half full. bit 0 (aehf) in the status0 register is set when bit 30 of one of the xwatthr registers changes, signifying one of these registers is half full. if the active power is positive, the watt-hour register becomes half full when it increments from 0x3fff ffff to 0x 4000 0000. if the active power is negative, the watt-hour register becomes half full when it decrements from 0xc000 0000 to 0xbfff ffff. similarly, bit 1 (faehf) in status0 register, is set when bit 30 of one of the xfwatthr registers changes, signifying one of these registers is half full. setting bits[1:0] in the mask0 register enable the faehf and aehf interrupts, respectively. if enabled, the irq0 pin is set low and the status bit is set to 1 whenever one of the energy registers, xwatthr (for the aehf interrupt) or xfwatthr (for the faehf interrupt), become half full. the status bit is cleared and the irq0 pin is set to logic high by writing to the status0 register with the corresponding bit set to 1. setting bit 6 (rstread) of the lcycmode register enables a read-with-reset for all watt-hour accumulation registers, that is, the registers are reset to 0 after a read operation. integration time under steady load the discrete time sample period (t) for the accumulation register is 976.5625 ns (1.024mhz frequency). with full-scale sinusoidal signals on the analog inputs and the watt gain registers set to 0x00000, the average word value from each lpf2 is pmax = 27,059,678 = 0x19ce5de. if the wthr register threshold is set at 3, its minimum recommended value, the first stage accumulator generates a pulse that is added to watt-hour registers every sec531.14 10024.1 23 6 27 = the maximum value that can be stored in the watt-hour accumulation register before it overflows is 2 31 ? 1 or 0x7fffffff. the integration time is calculated as time = 0x7fff,ffff 14.531 s = 8 hr 40 min 6 sec (28)
ade7880 data sheet rev. a | page 48 of 104 energy accumulation modes the active power is accumulated in each watt-hour accumulation 32-bit register (awatthr, bwatthr, c wat t h r , a f wat t h r , b f wat t h r , a n d c f wat t h r ) according to the configuration of bit 5 and bit 4 (consel bits) in the accmode register. the various configurations are described in table 14 . table 14. inputs to watt-hour accumulation registers consel awat thr bwat thr cwat thr 00 va ia vb ib vc ic 01 va ia vb ib vb = va C vc 1 vc ic 10 va ia vb ib vc ic vb = ?va ? vc 11 va ia vb ib vc ic vb = ?va 1 in a 3-phase three wire case (consel[1:0] = 01), the ade7880 computes the rms value of the line voltage between phase a and phase c and stores the result into bvrms register (see the voltage rms in 3-phase three wire delta configurations section). consequently, the ade7880 computes powers associated with phase b that do not ha ve physical meaning. to avoid any errors in the frequency output pins (cf1, cf2, or cf3) related to the powers associated with phase b, disable the contribution of phase b to the energy-to- frequency converters by setting bits termsel1[1] or termsel2[1] or termsel3[1] to 0 in the compmode register (see the energy-to-frequency conversion section). depending on the polyphase meter service, choose the appro- priate formula to calculate the active energy. the american ansi c12.10 standard defines the different configurations of the meter. table 15 describes which mode to choose in these various configurations. table 15. meter form configuration ansi meter form configuration consel 5s/13s 3-wire delta 01 6s/14s 4-wire wye 10 8s/15s 4-wire delta 11 9s/16s 4-wire wye 00 bits[1:0] (wattacc[1:0]) in the accmode register determine how the active power is accumulated in the watt-hour registers and how the cf frequency output can be generated as a function of the total and fundamental active powers. see the energy-to-frequency conversion section for details. line cycle active energy accumulation mode in line cycle energy accumulation mode, the energy accumula- tion is synchronized to the voltage channel zero crossings such that active energy is accumulated over an integral number of half line cycles. the advantage of summing the active energy over an integer number of line cycles is that the sinusoidal compo- nent in the active energy is reduced to 0. this eliminates any ripple in the energy calculation and allows the energy to be accumulated accurately over a shorter time. by using the line cycle energy accumulation mode, the energy calibration can be greatly simplified, and the time required to calibrate the meter can be significantly reduced. in line cycle energy accumulation mode, the ade7880 transfers the active energy accumulated in the 32-bit internal accumulation registers into the xwathhr or xfwatthr registers after an integral number of line cycles, as shown in figure 76 . the number of half line cycles is specified in the linecyc register. the line cycle energy accumulation mode is activated by setting bit 0 (lwatt) in the lcycmode register. the energy accu- mulation over an integer number of half line cycles is written to the watt-hour accumulation registers after linecyc number of half line cycles is detected. when using the line cycle accumulation mode, the bit 6 (rstread) of the lcycmode register should be set to logic 0 because the read with reset of watt-hour registers is not available in this mode. phase a, phase b, and phase c zero crossings are, respectively, included when counting the number of half line cycles by setting bits[5:3] (zxsel[x]) in the lcycmode register. any combi- nation of the zero crossings from all three phases can be used for counting the zero crossing. select only one phase at a time for inclusion in the zero crossings count during calibration. zero- crossing detection (phase a) zero- crossing detection (phase b) calibration control zero- crossing detection (phase c) linecyc[15:0] awatthr[31:0] zxsel[0] in lcycmode[7:0] zxsel[1] in lcycmode[7:0] zxsel[2] in lcycmode[7:0] o utput from lpf2 awgain awattos internal accumulator threshold 32-bit register wthr 34 27 26 0 0 10193-051 figure 76. line cycle active energy accumulation mode the number of zero crossings is specified by the linecyc 16-bit unsigned register. the ade7880 can accumulate active power for up to 65,535 combined zero crossings. note that the internal zero-crossing counter is always active. by setting bit 0 (lwatt) in the lcycmode register, the first energy accumulation result is, therefore, incorrect. writing to the linecyc register when the lwatt bit is set resets the zero-crossing counter, thus ensuring that the first energy accumulation result is accurate. at the end of an energy calibration cycle, bit 5 (lenergy) in the status0 register is set. if the corresponding mask bit in the mask0 interrupt mask register is enabled, the irq0 pin also goes active low. the status bit is cleared and the irq0 pin is
data sheet ade7880 rev. a | page 49 of 104 set to high again by writing to the status0 register with the corresponding bit set to 1. because the active power is integrated on an integer number of half-line cycles in this mode, the sinusoidal components are reduced to 0, eliminating any ripple in the energy calculation. therefore, total energy accumulated using the line cycle accumulation mode is () = + = = 1 k kk ntt t ivntdttpe cos( k C k ) (29) where nt is the accumulation time. note that line cycle active energy accumulation uses the same signal path as the active energy accumulation. the lsb size of these two methods is equivalent. fundamental reactive power calculation the ade7880 computes the fundamental reactive power, the power determined only by the fundamental components of the voltages and currents. the ade7880 also computes the harmonic reactive powers, the reactive powers determined by the harmonic components of the voltages and currents. see harmonics calculations section for details. a load that contains a reactive element (inductor or capacitor) produces a phase difference between the applied ac voltage and the resulting current. the power associated with reactive elements is called reactive power, and its unit is var. reactive power is defined as the product of the voltage and current waveforms when all harmonic components of one of these signals are phase shifted by 90. equation 31 is an example of the instantaneous reactive power signal in an ac system when the phase of the current channel is shifted by +90. = = 1 2)( k k vtv sin( kt + k ) (30) () k k k tkiti + = = sin2)( 1 (31) ? ? ? ? ? ? ++ = = 2 sin2)(' 1 tkiti k k k where i(t) is the current waveform with all harmonic components phase shifted by 90. next, the instantaneous reactive power, q(t), can be expressed as q(t) = v(t) i ? (t) (32) = = 1 2 )( k kk ivtq sin( kt + k ) sin( kt + k + 2 ) + 2sin(kt + k ) sin( mt + m + = mk mk m k iv 1, 2 ) note that q ( t ) can be rewritten as = = 1 )( k kk ivtq { cos ( k ? k ? 2 ) ? cos ( 2 kt + k + k + 2 ) } + = mk mk m k iv 1, { cos [ ( k C m ) t + k ? k ? 2 ] ? cos [ ( k + m ) t + k + k + 2 ] } (33) the average total reactive power over an integral number of line cycles (n) is shown in equation 34. () = = = nt k kk ivdttq nt q 0 1 1 cos( k C k ? 2 ) (34) = = 1 k kk ivq sin( k C k ) where: t is the period of the line cycle. q is referred to as the total reactive power. note that the total reactive power is equal to the dc component of the instantaneous reactive power signal q(t) in equation 32, that is, = 1 k kk iv sin( k C k ) this is the relationship used to calculate the total reactive power for each phase. the instantaneous reactive power signal, q(t), is generated by multiplying each harmonic of the voltage signals by the 90 phase-shifted corresponding harmonic of the current in each phase. the expression of fundamental reactive power is obtained from equation 33 with k = 1, as follows: fq = v 1 i 1 sin( 1 C 1 ) the ade7880 computes the fundamental reactive power using a proprietary algorithm that requires some initialization function of the frequency of the network and its nominal voltage measured in the voltage channel. these initializations are introduced in the active power calculation section and are common for both fundamental active and reactive powers. the ade7880 stores the instantaneous fundamental phase r e a c t i v e p o w e r s i nt o t h e a f va r , b f va r , a n d c f va r r e g i s t e r s . their equation is = fsfs i i u u xfvar 11 sin( 1 C 1 ) pmax 4 2 1 (35) where: u fs , i fs are the rms values of the phase voltage and current when the adc inputs are at full scale. pmax = 27,059,678, the instantaneous power computed when the adc inputs are at full scale and in phase. the xfvar waveform registers are not mapped with an address in the register space and can be accessed only through hsdc port in the waveform sampling mode (see waveform sampling mode section for details). fundamental reactive power information is also available through the harmonic calculations of the ade7880 (see harmonics calculations section for details).
ade7880 data sheet rev. a | page 50 of 104 fundamental reactive power offset calibration table 16 presents the settling time for the fundamental reactive power measurement, which is the time it takes the power to reflect the value at the input of the ade7880 . the ade7880 provides a fundamental reactive power offset register on each phase. the afvaros, bfvaros, and cfvaros registers compensate the offsets in the fundamental reactive power calculations. these are signed twos complement, 24-bit registers that are used to remove offsets in the fundamental reactive power calculations. an offset can exist in the power calculation due to crosstalk between channels on the pcb or in the chip itself. the resolution of the registers is the same as for the active power offset registers (see the active power offset calibration section). table 16. settling time for fundamental reactive power input signals 63 pma 100 pma 375 ms 875 ms fundamental reactive pow er gain calibration the average fundamental reactive power from the lpf output in each phase can be scaled by 100% by writing to one of the phases var gain 24-bit register (apgain, bpgain, or cpgain). note that these registers are the same gain registers used to compensate the other powers computed by the ade7880 . see the active power gain calibration section for details on these registers. as stated in the current waveform gain registers section, the serial ports of the ade7880 work on 32-, 16-, or 8-bit words and the dsp works on 28 bits. similar to the registers presented in figure 43 , t h e a f va r o s , b f va r o s , a n d c f va r o s 2 4 - b i t signed registers are accessed as 32-bit registers with the four msbs padded with 0s and sign extended to 28 bits. internal accumulator threshold hpfen bit config3[0] hpf digital signal processor aigain avgain hpfen bit config3[0] digital integrator hpf va ia fundamental reactive power algorithm apgain afvaros aphcal 2 4 afvar : varthr 34 27 26 0 0 32-bit register afvarhr[31:0] revfrpa bit in status0[31:0] 10193-052 figure 77. fundamental reactive energy accumulation
data sheet ade7880 rev. a | page 51 of 104 sign of fundamental reac tive power calculation note that the fundamental reactive power is a signed calculation. table 17 summarizes the relationship between the phase difference between the voltage and the current and the sign of the resulting reactive power calculation. the ade7880 has sign detection circuitry for reactive power calculations that can monitor the fundamental reactive powers. as described in the fundamental reactive energy calculation section, the reactive energy accumulation is executed in two stages. every time a sign change is detected in the energy accumulation at the end of the first stage, that is, after the energy accumulated into the internal accumulator reaches the varthr register threshold, a dedicated interrupt is triggered. the sign of each phase reactive power can be read in the phsign register. bits[12:10] (revfrpc, revfrpb, and revfrpa, respect- tively) in the status0 register are set when a sign change occurs in the fundamental reactive power. bits[6:4] (cfvarsign, bfvarsign, and afvarsign, respectively) in the phsign register are set simultaneously with the revfrpc, revfrpb, and revfrpa bits. they indicate the sign of the fundamental reactive power. when they are 0, the reactive power is positive. when they are 1, the reactive power is negative. bit revfrpx of the status0 register and bit xfvarsign in the phsign register refer to the reactive power of phase x. setting bits[12:10] in the mask0 register enables the revfrpc, revfrpb, and revfrpa interrupts, respectively. if enabled, the irq0 pin is set low and the status bit is set to 1 whenever a change of sign occurs. to find the phase that triggered the interrupt, the phsign register is read immediately after read- ing the status0 register. next, the status bit is cleared and the irq0 pin is set to high by writing to the status0 register with the corresponding bit set to 1. table 17. sign of reactive power calculation 1 sign of reactive power between 0 to +180 positive between ?180 to 0 negative 1 is defined as the phase angle of the voltage signal minus the current signal; that is, is positive if the load is inductive and negative if the load is capacitive. fundamental reactive energy calculation fundamental reactive energy is defined as the integral of fundamental reactive power. reactive energy = q(t)dt (36) the fundamental reactive energy accumulation is always a signed operation. negative energy is subtracted from the reactive energy contents. similar to active power, the ade7880 achieves the integration of the reactive power signal in two stages (see figure 77 ). ? the first stage accumulates the instantaneous phase fundamental reactive power at 1.024 mhz, although they are computed by the dsp at 8 khz rate. every time a threshold is reached, a pulse is generated and the threshold is subtracted from the internal register. the sign of the energy in this moment is considered the sign of the reactive power (see the sign of fundamental reactive power calculation section for details). ? the second stage consists in accumulating the pulses generated after the first stage into internal 32-bit accumulation registers. the content of these registers is transferred to the var-hour registers (xfvarhr) when these registers are accessed. afwatthr, bfwatthr, and cfwatthr represent phase fundamental reactive energies. figure 77 explains this process. the threshold is formed by concatenating the varthr 8-bit unsigned register to 27 bits equal to 0 and it is introduced by the user. its value depends on how much energy is assigned to one lsb of var-hour registers. supposing a derivative of a volt ampere reactive hour (varh) [10 n varh] where n is an integer, is desired as one lsb of the varhr register, the varthr register can be computed using the following equation: 27 2 103600 = (37) where: pmax = 27,059,678 = 0x19ce5de, the instantaneous power computed when the adc inputs are at full scale. f s = 1.024 mhz, the frequency at which every instantaneous power computed by the dsp at 8 khz is accumulated. u fs , i fs are the rms values of phase voltages and currents when the adc inputs are at full scale. varthr register is an 8-bit unsigned number, so its maximum value is 2 8 ? 1. its default value is 0x3. values lower than 3, that is 2 or 1 should be avoided and 0 should never be used as the threshold must be a non-zero value. this discrete time accumulation or summation is equivalent to integration in continuous time, shown in equation 38: () () ? ? ? ? ? ? == = 0 0t lim n tntq dttqergy reactiveen (38) where: n is the discrete time sample number. t is the sample period.
ade7880 data sheet rev. a | page 52 of 104 on the ade7880 , the fundamental phase reactive powers are accumulated in the afvarhr, bfvarhr, and cfvarhr 32- bit signed registers. the reactive energy register content can roll over to full-scale negative (0x80000000) and continue increasing in value when the reactive power is positive. conversely, if the reactive power is negative, the energy register underflows to full-scale positive (0x7fffffff) and continues to decrease in value. the ade7880 provides a status flag to signal when one of the xfvarhr registers is half full. bit 3 (frehf) in the status0 register is set when bit 30 of one of the xfvarhr registers changes, signifying one of these registers is half full. if the reactive power is positive, the var-hour register becomes half full when it increments from 0x3fff ffff to 0x4000 0000. if the reactive power is negative, the var-hour register becomes half full when it decrements from 0xc000 0000 to 0xbfff ffff. setting bit3 in the mask0 register enables the frehf interrupt. if enabled, the irq0 pin is set low and the status bit is set to 1 whenever one of the energy registers, xfvarhr, becomes half full. the status bit is cleared and the irq0 pin is set to high by writing to the status0 register with the corresponding bit set to 1. setting bit 6 (rstread) of the lcycmode register enables a read-with-reset for all var-hour accumulation registers, that is, the registers are reset to 0 after a read operation. integration time under steady load the discrete time sample period (t) for the accumulation register is 976.5625 ns (1.024 mhz frequency). with full-scale sinusoidal signals on the analog inputs and a 90 phase difference between the voltage and the current signal (the largest possible reactive power), the average word value representing the reactive power is pmax = 27,059,678 = 0x19ce5de. if the varthr threshold is set at 3, its minimum recommended value, the first stage accumulator generates a pulse that is added to var-hour registers every sec531.14 10024.1 23 6 27 = pmax the maximum value that can be stored in the var-hour accumulation register before it overflows is 2 31 ? 1 or 0x7fffffff. the integration time is calculated as time = 0x7fff,ffff 14.531 s = 8 hr 40 min 6 sec (39) energy accumulation modes the fundamental reactive power accumulated in each var-hour accumulation 32-bit register (afvarhr, bfvarhr, and cfvarhr) depends on the configuration of bits[5:4] (consel[1:0]) in the accmode register, in correlation with the watt-hour registers. the different configurations are described in table 18 . note that ia /ib /ic are the phase- shifted current waveforms. table 18. inputs to var-hour accumulation registers consel[1:0] afvarhr bfvarhr cfvarhr 00 va ia vb ib vc ic 01 va ia vb ib vb = va ? vc 1 vc ic 10 va ia vb ib vc x ic vb = ?va ? vc 11 va ia vb ib vc ic vb = ?va 1 in a 3-phase three wire case (consel[1:0] = 01), the ade7880 computes the rms value of the line voltage between phases a and c and stores the result into bvrms register (see the voltage rms in 3-phas e three wire delta configurations section). consequently, the ade7880 computes powers associated with phase b that do not ha ve physical meaning. to avoid any errors in the frequency output pins (cf1, cf2, or cf3) related to the powers associated with phase b, disable the contribution of phase b to the energy to frequency converters by setting bits termsel1[1] or termsel2[1] or termsel3[1] to 0 in compmode register (see the energy-to-frequency conversion section). bits[3:2] (varacc[1:0]) in the accmode register determine how the reactive power is accumulated in the var-hour registers and how the cf frequency output can be generated function of total and fundamental active and reactive powers. see the energy- to-frequency conversion section for details. line cycle reactive energy accumulation mode as mentioned in the line cycle active energy accumulation mode section, in line cycle energy accumulation mode, the energy accumulation can be synchronized to the voltage channel zero crossings so that reactive energy can be accumulated over an integral number of half line cycles. in this mode, the ade7880 transfers the reactive energy accumulated in the 32-bit internal accumulation registers into the xfvarhr registers after an integral number of line cycles, as shown in figure 78 . the number of half line cycles is specified in the linecyc register. the line cycle reactive energy accumulation mode is activated by setting bit 1 (lvar) in the lcycmode register. the fundamental reactive energy accumulated over an integer number of half line cycles or zero crossings is available in the var- hour accumulation registers after the number of zero crossings specified in the linecyc register is detected. when using the line cycle accumulation mode, bit 6 (rstread) of the lcycmode register should be set to logic 0 because a read with the reset of var-hour registers is not available in this mode.
data sheet ade7880 rev. a | page 53 of 104 zero- crossing detection (phase a) zero- crossing detection (phase b) calibration control zero- crossing detection (phase c) linecyc[15:0] afvarhr[31:0] zxsel[0] in lcycmode[7:0] zxsel[1] in lcycmode[7:0] zxsel[2] in lcycmode[7:0] output from fundamental reactive power algorithm apgain afvaros internal accumulator threshold 32-bit register varthr 34 27 26 0 0 10193-053 figure 78. line cycle fundamental reactive energy accumulation mode phase a, phase b, and phase c zero crossings are, respectively, included when counting the number of half line cycles by setting bits[5:3] (zxsel[x]) in the lcycmode register. any combination of the zero crossings from all three phases can be used for counting the zero crossing. select only one phase at a time for inclusion in the zero-crossings count during calibration. for details on setting the linecyc register and the bit 5 (lenergy) in the mask0 interrupt mask register associated with the line cycle accumulation mode, see the line cycle active energy accumulation mode section. apparent power calculation apparent power is defined as the maximum active power that can be delivered to a load. one way to obtain the apparent power is by multiplying the voltage rms value by the current rms value (also called the arithmetic apparent power). s = v rms i rms (40) where: s is the apparent power. v rms and i rms are the rms voltage and current, respectively. the ade7880 computes the arithmetic apparent power on each phase. figure 79 illustrates the signal processing in each phase for the calculation of the apparent power in the ade7880 . because v rms and i rms contain all harmonic information, the apparent power computed by the ade7880 is total apparent power. the ade7880 computes fundamental and harmonic apparent powers determined by the fundamental and harmonic components of the voltages and currents. see the harmonics calculations section for details. the ade7880 stores the instantaneous phase apparent powers into the ava, bva, and cva registers. their equation is 4 2 1 = (41) where: u, i are the rms values of the phase voltage and current. u fs , i fs are the rms values of the phase voltage and current when the adc inputs are at full scale. pmax = 27,059,678, the instantaneous power computed when the adc inputs are at full scale and in phase. the xva[23:0] waveform registers may be accessed using various serial ports. refer to the waveform sampling mode section for more details. the ade7880 can compute the apparent power in an alternative way by multiplying the phase rms current by an rms voltage introduced externally. see the apparent power calculation using vnom section for details. internal accumulator threshold digital signal processor apgain 2 4 ava : vathr 34 27 26 0 0 32-bit register avahr[31:0] airms avrms 10193-054 figure 79. apparent power data flow and apparent energy accumulation
ade7880 data sheet rev. a | page 54 of 104 apparent power gain calibration the average apparent power result in each phase can be scaled by 100% by writing to one of the phases pgain 24-bit registers (apgain, bpgain, or cpgain). note that these registers are the same gain registers used to compensate the other powers computed by the ade7880 . see the active power gain calibration section for details on these registers. apparent power o ffset calibration each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value (see the root mean square measurement section). the voltage and current rms values are multiplied together in the apparent power signal processing. as no additional offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal processing. the offset compensation of the apparent power measurement in each phase is accomplished by calibrating each individual rms measurement. apparent power calculation using vnom the ade7880 can compute the apparent power by multiplying the phase rms current by an rms voltage introduced externally in the vnom 24-bit signed register. when one of bits[13:11] (vnomcen, vnomben, or vnomaen) in the compmode register is set to 1, the apparent power in the corresponding phase (phase x for vnomxen) is computed in this way. when the vnomxen bits are cleared to 0, the default value, then the arithmetic apparent power is computed. the vnom register contains a number determined by u, the desired rms voltage, and u fs , the rms value of the phase voltage when the adc inputs are at full scale: 572,766,3 = fs u u vnom (42) where u is the nominal phase rms voltage. as stated in the current waveform gain registers , the serial ports of the ade7880 work on 32-, 16-, or 8-bit words. similar to the register presented in figure 57 , the vnom 24-bit signed register is accessed as a 32-bit register with the eight msbs padded with 0s. apparent energy calculation apparent energy is defined as the integral of apparent power. apparent energy = s ( t ) dt (43) similar to active and reactive powers, the ade7880 achieves the integration of the apparent power signal in two stages (see figure 79 ). the first stage accumulates the instantaneous apparent power at 1.024 mhz, although they are computed by the dsp at 8 khz rate. every time a threshold is reached, a pulse is generated and the threshold is subtracted from the internal register. the second stage consists in accumulating the pulses generated after the first stage into internal 32-bit accumulation registers. the content of these registers is transferred to the va- hour registers, xvahr, when these registers are accessed. figure 79 illustrates this process. the threshold is formed by the vathr 8-bit unsigned register concatenated to 27 bits equal to 0. it is introduced by the user and is common for all phase total active and fundamental powers. its value depends on how much energy is assigned to one lsb of va-hour registers. when a derivative of apparent energy (vah) [10 n vah], where n is an integer, is desired as one lsb of the xvahr register, the xvathr register can be computed using the following equation: 27 2 103600 = fsfs n s iu fpmax vathr (44) where: pmax = 27,059,678 = 0x19ce5de, the instantaneous power computed when the adc inputs are at full scale. f s = 1.024 mhz, the frequency at which every instantaneous power computed by the dsp at 8 khz is accumulated. u fs , i fs are the rms values of phase voltages and currents when the adc inputs are at full scale. the vathr register is an 8-bit unsigned number, so its maximum value is 2 8 ? 1. its default value is 0x3. values lower than 3, that is 2 or 1 should be avoided and 0 should never be used as the threshold must be a non-zero value. this discrete time accumulation or summation is equivalent to integration in continuous time following the description in equation 45. () () ? ? ? ? ? ? == = 0 0t lim n tnts dttsergy apparenten (45) where: n is the discrete time sample number. t is the sample period. in the ade7880 , the phase apparent powers are accumulated in the avahr, bvahr, and cvahr 32-bit signed registers. the apparent energy register content can roll over to full-scale negative (0x80000000) and continue increasing in value when the apparent power is positive. conversely, if because of offset compensation in the rms data path, the apparent power is negative, the energy register underflows to full-scale positive (0x7fffffff) and continues to decrease in value. the ade7880 provides a status flag to signal when one of the xvahr registers is half full. bit 4 (vaehf) in the status0 register is set when bit 30 of one of the xvahr registers changes, signifying one of these registers is half full. as the apparent power is always positive and the xvahr registers are signed, the va-hour registers become half full when they increment from 0x3fffffff to 0x40000000. interrupts attached to bit vaehf in the status0 register can be enabled by setting bit 4 in the mask0 register. if enabled, the irq0 pin is set low and the status bit is set to 1 whenever one of the energy registers xvahr becomes half full. the status bit is cleared and the irq0 pin is set to high
data sheet ade7880 rev. a | page 55 of 104 by writing to the status0 register with the corresponding bit set to 1. setting bit 6 (rstread) of the lcycmode register enables a read-with-reset for all xvahr accumulation registers, that is, the registers are reset to 0 after a read operation. integration time under steady load the discrete time sample period for the accumulation register is 976.5625 ns (1.024 mhz frequency). with full-scale pure sinusoidal signals on the analog inputs, the average word value representing the apparent power is pmax. if the vathr threshold register is set at 3, its minimum recommended value, the first stage accumulator generates a pulse that is added to the xvahr registers every sec531.14 10024.1 23 6 27 = pmax the maximum value that can be stored in the xvahr accumulation register before it overflows is 2 31 ? 1 or 0x7fffffff. the integration time is calculated as time = 0x7fffffff 14.531 s = 8 hr 40 min 6 sec (46) energy accumulation mode the apparent power accumulated in each accumulation register depends on the configuration of bits[5:4] (consel[1:0]) in the accmode register. the various configurations are described in table 19 . table 19. inputs to va-hou r accumulation registers consel[1:0] avahr bvahr cvahr 00 avrms airms bvrms birms cvrms cirms 01 avrms airms bvrms birms vb = va C vc 1 cvrms cirms 10 avrms airms bvrms birms cvrms cirms vb = ?va ? vc 11 avrms airms bvrms birms cvrms cirms vb = ?va 1 in a 3-phase three wire ca se (consel[1:0] = 01), the ade7880 computes the rms value of the line voltage between phase a and phase c and stores the result into the bvrms register (see the voltage rms in 3-phase three wire delta configurations section). consequently, the ade7880 computes powers associated with phase b that do not ha ve physical meaning. to avoid any errors in the frequency output pins (cf1, cf2, or cf3) related to the powers associated with phase b, disable the contribution of phase b to the energy to frequency converters by setting bits termsel1[1] or termsel2[1] or termsel3[1] to 0 in compmode register (see the energy-to-frequency conversion section). line cycle apparent energy accumulation mode as described in the line cycle active energy accumulation mode section, in line cycle energy accumulation mode, the energy accumulation can be synchronized to the voltage channel zero crossings allowing apparent energy to be accumulated over an integral number of half line cycles. in this mode, the ade7880 transfers the apparent energy accumulated in the 32-bit internal accumulation registers into the xvahr registers after an integral number of line cycles, as shown in figure 80 . the number of half line cycles is specified in the linecyc register. zero- crossing detection (phase a) zero- crossing detection (phase b) calibration control zero- crossing detection (phase c) linecyc[15:0] zxsel[0] in lcycmode[7:0] zxsel[1] in lcycmode[7:0] zxsel[2] in lcycmode[7:0] internal accumulator threshold apgain vathr 34 27 26 0 0 32-bit register avahr[31:0] 10193-055 airms avrms figure 80. line cycle apparent energy accumulation mode the line cycle apparent energy accumulation mode is activated by setting bit 2 (lva) in the lcycmode register. the apparent energy accumulated over an integer number of zero crossings is written to the xvahr accumulation registers after the number of zero crossings specified in linecyc register is detected. when using the line cycle accumulation mode, set bit 6 (rstread) of the lcycmode register to logic 0 because a read with the reset of xvahr registers is not available in this mode. phase a, phase b, and phase c zero crossings are, respectively, included when counting the number of half line cycles by setting bits[5:3] (zxsel[x]) in the lcycmode register. any combi- nation of the zero crossings from all three phases can be used for counting the zero crossing. select only one phase at a time for inclusion in the zero-crossings count during calibration. for details on setting the linecyc register and bit 5 (lenergy) in the mask0 interrupt mask register associated with the line cycle accumulation mode, see the line cycle active energy accumulation mode section. power factor calculation the ade7880 provides a direct power factor measurement simultaneously on all phases. power factor in an ac circuit is defined as the ratio of the total active power flowing to the load to the apparent power. the absolute power factor measurement is defined in terms of leading or lagging referring to whether the current is leading or lagging the voltage waveform. when the current is leading the voltage, the load is capacitive and this is defined as a negative power factor. when the current is lagging the voltage, the load is inductive and this defined as a positive power factor. the relationship of the current to the voltage waveform is illustrated in figure 81 .
ade7880 data sheet rev. a | page 56 of 104 v i active (?) reactive (?) pf (+) capacitive: current leads voltage inductive: current lags voltage active (+) reactive (?) pf (?) active (?) reactive (+) pf (?) active (+) reactive (+) pf (+) = +60 pf = ?0.5 = ?60 pf = +0.5 10193-056 figure 81. capacitive and inductive loads as shown in figure 81 , the reactive power measurement is negative when the load is capacitive, and positive when the load is inductive. the sign of the reactive power can therefore be used to reflect the sign of the power factor. note that the ade7880 computes the fundamental reactive power, so its sign is used as the sign of the absolute power factor. if the fundamental reactive power is in no load state, then the sign of the power factor is the sign of the total active power. the mathematical definition of power factor is shown in equation 47: power factor = (sign fundamental reactive power) power apparent power activetotal (47) as previously mentioned, the ade7880 provides a power factor measurement on all phases simultaneously. these readings are provided into three 16-bit signed registers, apf (address 0xe609 ) for phase a, bpf (address 0xe60a) for phase b, and cpf (address 0xe60b) for phase c. the registers are signed twos complement register with the msb indicating the polarity of the power factor. each lsb of the apf, bpf, and cpf registers equates to a weight of 2 ?15 , hence the maximum register value of 0x7fff equating to a power factor value of 1. the minimum register value of 0x8000 corresponds to a power factor of ?1. if because of offset and gain calibrations, the power factor is outside the ?1 to +1 range, the result is set at ?1 or +1 depending on the sign of the fundamental reactive power. by default the instantaneous total phase active and apparent powers are used to calculate the power factor and the registers are updated at a rate of 8 khz. the sign bit is taken from the instantaneous fundamental phase reactive energy measurement on each phase. should a measurement with more averaging be required, the ade7880 provides an option of using the line cycle accumulation measurement on the active and apparent energies to determine the power factor. this option provides a more stable power factor reading. this mode is enabled by setting the pfmode bit (bit 7) in the lcycmode register (address 0xe702). when this mode is enabled the line cycle accumulation mode must be enabled on both the active and apparent energies. this is done by setting the xlwatt and xlva bits in the lcycmode register (address 0xe702). the update rate of the power factor measurement is now an integral number of half line cycles that can be programmed into the linecyc register (address 0xe60c). for full details on setting up the line cycle accumulation mode see the line cycle active energy accumulation mode and line cycle apparent energy accumulation mode sections. note that the power factor measurement is effected by the no load condition if it is enabled (see the no load condition section). if the apparent energy no load is true, then the power factor measurement is set to 1. if the no load condition based on total active and apparent energies is true, the power factor measurement is set at 0. the ade7880 also computes the power factor on the fundamental and harmonic components based on the fundamental and harmonic active, reactive and apparent powers. see the harmonics calculations section for details. harmonics calculations the ade7880 contains a harmonic engine that analyzes one phase at a time. harmonic information is computed with a no attenuation pass band of 2.8 khz (corresponding to a ?3 db bandwidth of 3.3 khz) and it is specified for line frequencies between 45 hz and 66 hz. neutral current can also be analyzed simultaneously with the sum of the phase currents. figure 82 presents a synthesized diagram of the harmonic engine, its settings and its output registers. theory of operation consider an nonsinusoidal ac system supplied by a voltage, v(t) that consumes the current i(t). then sin2)( 1 = = k k vtv ( kt + k ) (48) () ? + = = where: v k , i k are rms voltage and current, respectively, of each harmonic. k , k are the phase delays of each harmonic. is the angular velocity at the fundamental (line) frequency f. the ade7880 harmonics calculations are specified for line frequencies between 45 hz and 66 hz. the phase nominal voltage used as time base must have an amplitude greater than 20% of full scale. the number of harmonics n that can be analyzed within the 2.8 khz pass band is the whole number of 2800/f. the absolute maximum number of harmonics accepted by the ade7880 is 63. ? ? ? ? ? ? = , n63
data sheet ade7880 rev. a | page 57 of 104 when the ade7880 analyzes a phase, the following metering quantities are computed: ? fundamental phase current rms: i 1 ? fundamental phase voltage rms: v 1 ? rms of up to three harmonics of phase current: i x , i y , i z , x,y,z=2, 3,, n ? rms of up to three harmonics of phase voltage: v x , v y , v z , x,y,z=2, 3,, n ? fundamental phase active power p 1 = v 1 i 1 cos( 1 ? 1 ) ? fundamental phase reactive power q 1 = v 1 i 1 sin( 1 ? 1 ) ? fundamental phase apparent power s 1 = v 1 i 1 ? power factor of the fundamental ?? 1 1 1 1 sgn s p qpf ?? active power of up to three harmonics: p x = v x i x cos( x C x ), x=2, 3,, n p y = v y i y cos( y C y ), y=2, 3,, n p z = v z i z cos( z C z ), z=2, 3,, n ? reactive power of up to three harmonics: q x = v x i x sin( x C x ), x=2, 3,, n q y = v y i y sin( y C y ), y=2, 3,, n q z = v z i z sin( z C z ), z=2, 3,, n ? apparent power of up to three harmonics: s x = v x i x , x = 2, 3, , n s y = v y i y , y = 2 , 3, , n s z = v z i z , z = 2, 3, , n ? power factor of up to three harmonics: ?? x x x x s p qpf ?? sgn , x = 2, 3,, n ?? y y y y s p qpf ?? sgn , y = 2, 3,, n ?? z z z z s p qpf ?? sgn , z = 2, 3,, n ? total harmonic distortion of the phase current ?? 1 2 1 2 i ii thd i ? ? ? total harmonic distortion of the phase voltage ?? 1 2 1 2 v vv thd v ? ? ? harmonic distortion of up to three harmonics on the phase current 1 i i hd x i x ? , x = 2, 3,, n 1 i i hd y i y ? , y = 2, 3,, n 1 i i hd z i z ? , z = 2, 3,, n ? harmonic distortion of up to three harmonics on the phase voltage: 1 v v hd x v x ? , x = 2, 3,, n 1 v v hd y v y ? , y = 2, 3,, n 1 v v hd z v z ? , z = 2, 3,, n
data sheet ade7880 rev. a | page 58 of 104 ia, va ib, vb ic, vc in, isum hxwatt hywatt hzwatt fwatt hxvar hyvar hzvar fvar hxva hyva hzva fva hxvrms hyvrms hzvrms fvrms hxirms hyirms hzirms firms hxvhd hyvhd hzvhd vthd hxihd hyihd hzihd ithd hxpf hypf hzpf fpf ade7880 harmonic calculations hxvrms hyvrms hzvrms hxirms hyirms hzirms in results isum results hxvhd hyvhd hzvhd hxihd hyihd hzihd in results isum results hphase bits hconfig[2,1] select the phase being monitored output registers used when one of phases a, b, c is analyzed actphsel bits hconfig[9,8] select the phase used to as time base hx, hy, hz registers select the harmonics to monitor hrate bits hconfig[7:5] select the update rate of harmonic registers hstime bits hconfig[4,3] select the delay in triggering hready interrupt hrcfg bit hconfig[0] selects if hready flag in status0 is set immediately of after hstime output registers used when neutral current is analyzed 10193-057 figure 82. ade7880 harmonic engine block diagram w hen the neutral current and the sum of the three phase currents represented by isum register are analyzed, the following metering quantities are computed for both currents: ? rms of fundamental and of up to 2 harmonics or rms of up to three harmonics: i x , i y , i z , x, y, z = 1,2, 3,, n. ? harmonic distortions of the analyzed harmonics. configuring the harmonic calculations the ade7880 requires a time base provided by a phase voltage. bit 9 and bit 8 (actphsel) of hconfig[15:0]register select this phase voltage. if actphsel = 00, the phase a is used. if actphsel = 01, the phase b is used and if actphsel = 10, the phase c is used. if the phase voltage used as time base is down, select another phase, and the harmonic engine continues to work properly. the phase under analysis is selected by bit 2 and bit 1 (hphase) of hconfig[15:0]register. if hphase = 00, the phase a is monitored. if hphase = 01, the phase b is monitored and if hphase = 10, the phase c is monitored. if hphase = 11, the neutral current together with the sum of the phase currents represented by isum register are monitored. harmonic calculations when a phase is monitored when a phase is monitored, fundamental information together with information about up to three harmonics is computed. the indexes of the three additional harmonics simultaneously monitored by the ade7880 are provided by the 8-bit registers hx, hy, and hz. simply write the index of the harmonic into the register for that harmonic to be monitored. if the second harmonic is monitored, write 2. if harmonic 51 is desired, write 51. the fundamental components are always monitored, independent of the values written into hx, hy, or hz. therefore, if one of these registers is made equal to 1, the ade7880 monitors the fundamental components multiple times. the maximum index allowed in hx, hy, and hz registers is 63. the no attenuation pass band is 2.8 khz, corresponding to a ?3 db bandwidth of 3.3 khz, thus all harmonics of frequency lower than 2800 hz are supported without attenuation. the rms of the phase voltage and phase current fundamental components are stored into fvrms and firms 24-bit signed registers. the associated data path is presented in figure 83 . similar to the rms current and voltage rms data paths presented in root mean square measurement section, the data path contains 24-bit signed offset compensation registers xirmsos, xvrmsos, x = a, b, c for each phase quantity. the rms of the phase current and phase voltage three harmonic components are stored into hxvrms, hxirms, hyvrms, hyirms, hzvrms, and hzirms 24-bit signed registers. the associated data path is presented in figure 84 and contains the following 24-bit signed offset compensation registers: hxirmsos, hyirmsos, hzirmsos, hxvrmsos, hyvrmsos, and hzvrmsos. it is recommended to leave the offset compensation registers at 0, the default value.
data sheet ade7880 rev. a | page 59 of 104 table 20. harmonic engine outputs when phase a, phase b, or phase c is analyzed and the registers where the values are stored quantity definition ade7880 register rms of the fundamental component v1, i1 fvrms, firms v x , i x , x = 2, 3,, n hxvrms, hxirms v y , i y , y = 2, 3,, n hyvrms, hyirms rms of a harmonic component v z , i z , z = 2, 3,, n hzvrms, hzirms active power of the fundamental component p 1 = v 1 i 1 cos( 1 ? 1 ) fwatt p x = v x i x cos( x C x ), x = 2, 3,, n hxwatt p y = v y i y cos( y C y ), y = 2, 3,, n hywatt active power of a harmonic component p z = v z i z cos( z C z ), z = 2, 3,, n hzwatt reactive power of the fundamental component q 1 = v 1 i 1 sin( 1 ? 1 ) fvar q x = v x i x sin( 1 ? 1 ), x = 2, 3,, n hxvar q y = v y i y sin( y C y ), y = 2, 3,, n hyvar reactive power of a harmonic component q z = v z i z sin( z C z ), z = 2, 3,, n hzvar apparent power of the fundamental component s 1 = v 1 i 1 fva s x = v x i x , x = 2, 3, , n hxva s y = v y i y , y = 2, 3, , n hyva apparent power of a harmonic component s z = v z i z , z = 2, 3, , n hzva fpf power factor of the fundamental component () 1 1 1 1 sgn s p qpf = () x x x x s p qpf = sgn , x = 2, 3,, n hxpf () y y y y s p qpf = sgn , y = 2, 3,, n hypf power factor of a harmonic component () z z z z s p qpf = sgn , z = 2, 3,, n hzpf () 1 2 1 2 v vv thd v ? = vthd total harmonic distortion () 1 2 1 2 i ii thd i ? = ithd hxvhd, hxihd 1 v v hd x v x = , 1 i i hd x i x = , x = 2, 3,, n 1 v v hd y v y = , 1 i i hd y i y = ,y = 2, 3,, n hyvhd, hyihd harmonic distortion of a harmonic component 1 v v hd z v z = , 1 i i hd z i z = ,z = 2, 3,, n hzvhd, hzihd
ade7880 data sheet rev. a | page 60 of 104 table 21. harmonic engine outputs when ne utral current and isum are analyzed and the registers where the values are stored quantity definition ade7880 register i x , x = 1,2, 3,, n hxirms i y , y = 1,2, 3,, n hyirms rms of a harmonic component (including the fundamental) of the neutral current i z , z = 1,2, 3,, n hzirms isumx, x = 1,2,3,,n hxvrms isumy, y = 1,2,3,,n hyvrms rms of a harmonic component (including the fundamental) of isum isumz, z = 1,2,3,,n hzvrms hxihd 1 i i hd x i x = , x = 1,2,3,,n 1 i i hd y i y = , y = 1,2,3,,n hyihd harmonic distortion of a harmonic compon ent (including the fundamental) of the neutral current (note that the hx register must be set to 1 for these calculations to be executed) 1 i i hd z i z = , z = 1,2,3,,n hzihd hxvhd 1 isum isum hd x isum x = , x = 1,2,3,,n 1 isum isum hd y isum y = , y = 1,2,3,,n hyvhd harmonic distortion of a harmonic compon ent (including the fundamental) of isum. (note that the hx register must be set to 1 for these calculations to be executed) 1 isum isum hd z isum z = , z = 1,2,3,,n hzvhd
data sheet ade7880 rev. a | page 61 of 104 airmsos 2 7 birmsos 2 7 cirmsos 2 7 hphase bits hconfig[2, 1] select the phase being monitored avrmsos 2 7 bvrmsos 2 7 cvrmsos 2 7 hphase bits hconfig[2, 1] select the phase being monitored fundamental components calculations firms hphase bits hconfig[2, 1] select the gain being used apgain or bpgain or cpgain fva fvrms 10193-058 figure 83. fundamental rms signal processing the active, reactive, and apparent powers of the fundamental component are stored into the fwatt, fvar, and fva 24-bit signed registers. figure 85 presents the associated data path. the active, reactive and apparent powers of the 3 harmonic components are stored into the hxwatt, hxvar, hxva, hywatt, hyvar, hyva, hzwatt, hzvar, and hzva 24-bit signed registers. figure 86 presents the associated data path. the power factor of the fundamental component is stored into fpf 24-bit signed register. the power factors of the three harmonic components are stored into the hxpf, hypf, and hzpf 24-bit signed registers. the total harmonic distortion ratios computed using the rms of the fundamental components and the rms of the phase current and the phase voltage (see root mean square chapter for details about these measurements) are stored into the vthd and ithd 24-bit registers in 3.21 signed format. this means the ratios are limited to +3.9999 and all greater results are clamped to it.
ade7880 data sheet rev. a | page 62 of 104 harmonic components calculations hxirmsos 2 7 hxirms hyirmsos 2 7 hyirms hzirmsos 2 7 hzirms hxvrmsos 2 7 hxvrms hyvrmsos 2 7 hyvrms hxvrmsos 2 7 hzvrms 10193-059 figure 84. harmonic rms signal processing fundamental components calculations apgain afwattos 2 2 bpgain bfwattos 2 2 cpgain cfwattos 2 2 hphase bits hconfig[2, 1] select the phase being monitored fwatt apgain afvaros 2 2 bpgain bfvaros 2 2 cpgain cfvaros 2 2 hphase bits hconfig[2, 1] select the phase being monitored fvar 10193-060 figure 85. fundamental active and reactive powers signal processing
data sheet ade7880 rev. a | page 63 of 104 harmonic components calculations hpgain hxwattos 2 2 hxwatt hpgain hywattos 2 2 hywatt hpgain hzwattos 2 2 hzwatt hpgain hxvaros 2 2 hxvar hpgain hyvaros 2 2 hyvar hpgain hzvaros 2 2 hzvar 10193-061 figure 86. harmonic active and reactive powers signal processing the harmonic distortions of the three harmonic components are stored into the hxvhd, hxihd, hyvhd, hyihd, hzvhd, and hzihd 24-bit registers in 3.21 signed format. this means the ratios are limited to +3.9999 and all greater results are clamped to it. as a reference, table 20 presents the ade7880 harmonic engine outputs when one phase is analyzed and the registers in which the outputs are stored. harmonic calculations when the neutral is monitored when the neutral current and the sum of phase currents are monitored, only the harmonic rms related registers are updated. the registers hx, hy and hz identify the index of the harmonic, including the fundamental. when a phase is analyzed, the fundamental rms values are calculated continuously and the results are stored in dedicated registers firms and fvrms. when the neutral is analyzed, the fundamental information is calculated by setting one of the harmonic index registers hx, hy or hz to 1 and the results are stored in harmonic registers. the maximum index allowed in hx, hy and hz registers is 63. the no attenuation pass band is 2.8 khz, corresponding to a ?3 db bandwidth of 3.3 khz, thus all harmonics of frequency lower than 2800 hz are supported without attenuation. hxirms, hyirms and hzirms registers contain the harmonic rms components of the neutral current and hxvrms, hyvrms and hzvrms registers contain the harmonic rms components of isum. note that in this case, the rms of the fundamental component is not computed into firms or fvrms registers, but it is computed if one of the index registers hx, hy and hz is initialized with 1. if the hx register is initialized to 1, the ade7880 computes the harmonic distortions of the other harmonics identified into hy hyvhd, hyihd, hzvhd, and hzihd 24-bit registers. the distortions of the neutral current are saved into hyihd and hzihd registers and the distortions of the isum are stored into the hyvhd and hzvhd registers. as hx is set to 1, th hxihd and hxvhd registers contain 0x1fffff, a number representing 1 in 3.21 signed format. as a reference, table 21 presents the and hz registers and stores them in 3.21 signed format into the e de7880 harmonic engine ate rate from isters, ic engine output registers is s t o ways to manage the harmonic fg) a outputs when the neutral current and isum are analyzed and the registers in which the outputs are stored. configuring harmonic calculations upd the ade7880 harmonic engine functions at 8 khz rate. the moment the hconfig register is initialized and the harmonic indexes are set in the hx, hy and hz index reg the ade7880 calculations take typically 750 ms to settle within the specification parameters. the update rate of the harmon managed by bits[7:5] (hrate) in hconfig register and i independent of the engines calculations rate of 8 khz. the defaul value of 000 means the registers are updated every 125 sec (8 khz rate). other update periods are: 250 sec (hrate = 001), 1 ms (010), 16 ms (011), 128 ms (100), 512 ms (101), 1.024 sec (110). if hrate bits are 111, then the harmonic calculations are disabled. the ade7880 provides tw computations. the first approach, enabled when bit 0 (hrc of hconfig register is cleared to its default value of 0, sets bit 19 (hready) in status0 register to 1 after a certain period of time and then every time the harmonic calculations are updated at hrate frequency. this allows an external microcontroller to access the harmonic calculations only after they have settled. the time period is determined by the state of bits[4:3] (hstime) in the hconfig register. the default value of 01 sets the time
ade7880 data sheet rev. a | page 64 of 104 d approach, enabled when bit 0 (hrcfg) of ns are to 750 ms, the settling time of the harmonic calculations. other possible values are 500 ms (hstime = 00), 1 sec (10) and 1250 ms (11). the secon hconfig register is set to 1, sets bit 19 (hready) in status0 register to 1 every time the harmonic calculatio updated at the update frequency determined by hrate bits without waiting for the harmonic calculations to settle. this allows an external microcontroller to access the harmonic calculations immediately after they have been started. if the corresponding mask bit in the mask0 interrupt mask register is enabled, the irq pin also goes active low. the status bit is cleared and the pin irq is set to high again by writing to the status0 register with the corresponding bit set to 1. additionally, the ade7880 provides a periodical outpu t signal c y ady er s e registers in which e ng harmonic ded approach to managing the ade7880 ig register. set the s d by setting hx, hy register bits. harmonic formation is wa d voltage waveform, called hready at the cf2/hready pin synchronous to the moment the harmonic calculations are updated in the harmoni registers. this functionality is chosen if bit 2 (cf2dis) is set to 1 in the config register. if cf2dis is set to 0 (default value), the cf2 energy to frequency converter output is provided at cf2/hready pin. the default state of this signal is high. ever time the harmonic registers are updated based on hrate bits in hconfig register, the signal hready goes low for approximately 10 sec and then goes back high. if bit 0 (hrcfg) in the hconfig register is 0, that is the hre bit in the status1 register is set to 1 every hrate period right after the harmonic calculations have started, the signal hready toggles high, low and back synchronously. if the hrcfg bit is 1, that is, bit hready in the status1 regist is set to 1 after the hstime period, the hready signal toggle high, low and back synchronously. the hready signal allows fast access to the harmonic registers without having to use hready interrupt in mask1 register. in order to facilitate the fast reading of th the harmonic calculations are stored, a special burst registers reading has been implemented in the serial interfaces. see the i 2 c read operation of harmonic calculations registers and th spi read operation sections for details. recommended approach to managi calculations the recommen h armonic calculations is the following: ? set up bit 2 (cf2dis) in the conf c f2dis bit to 1 to use the cf2/hready pin to signal when the harmonic calculations have settled and are updated. the high to low transition of hready signal indicates when to read the harmonic registers. use the burst reading mode to read the harmonic registers as it i the most efficient way to read them. ? choose the harmonics to be monitore a nd hz appropriately. ? select all the hconfig ? initialize the gain registers used in the c alculations. leave the offset registers to 0. ? read the registers in which the harmonic in stored using the burst or regular reading mode at high to low transitions of cf2/hready pin. veform sampling mode the waveform samples of the current an the active, reactive, and apparent power outputs are stored every 125 s (8 khz rate) into 24-bit signed registers that can be accessed through various serial ports of the ade7880 . table 22 provides a list of registers and their descriptions. table 22. waveform registers list register description iawv phase a curre nt vawv phase a voltage ibwv phase b current vbwv phase b voltage icwv phase c current vcwv phase c voltage inwv neutral current ava phase a apparen t power bva phase b apparent power cva phase c apparent power awat t phase a active power bwatt phase b active power cwatt phase c active power bit 17 (d ready) i can be used to g ntains a high speed data capture (hsdc) port in the current waveform gain registers section, the ersion : cf1, cf2, n y n the status0 register signal when the registers listed in table 22 can be read usin i 2 c or spi serial ports. an interrupt attached to the flag can be enabled by setting bit 17 (dready) in the mask0 register. (see the digital signal processor section for more details on bit dready). the ade7880 co that is specially designed to provide fast access to the waveform sample registers. read the hsdc interface section for more details. as stated serial ports of the ade7880 work on 32-, 16-, or 8-bit words. all registers listed in table 22 are transmitted signed extended from 24 bits to 32 bits (see figure 44 ). energy-to-freque ncy conv the ade7880 provides three frequency output pins and cf3. the cf2 pin is multiplexed with the hready pin of the harmonic calculations block. when hready is enabled, the cf2 functionality is disabled at the pin. the cf3 pin is multiplexed with the hsclk pin of the hsdc interface. whe hsdc is enabled, the cf3 functionality is disabled at the pin. cf1 pin is always available. after initial calibration at manu- facturing, the manufacturer or end customer verifies the energ meter calibration. one convenient way to verify the meter calibration is to provide an output frequency proportional to the
data sheet ade7880 rev. a | page 65 of 104 the mputes the instantaneous values of all phase powers: ed ve active, reactive, or apparent powers under steady load conditions. this output frequency can provide a simple, single-wire, optically isolated interface to external calibration equipment. figure 87 illustrates the energy-to-frequency conversion in ade7880 . the dsp co total active, fundamental active, fundamental reactive, and apparent. the process in which the energy is sign accumulat in various xwatthr, xfvarhr, and xvahr registers has already been described in the energy calculation sections: acti energy calculation , fundamental reactive energy calculation , and apparent energy calculation . in the energy-to-frequency conversion process, the instantaneous powers generate signals at the frequency output pins (cf1, cf2, and cf3). one digital- to-frequency converter is used for every cfx pin. every converter sums certain phase powers and generates a signal proportional to the sum. two sets of bits decide what powers are converted. first, bits[2:0] (termsel1[2:0]), bits[5:3] (termsel2[2:0]), and bits[8:6] (termsel3[2:0]) of the compmode register decide which phases, or which combination of phases, are added. the termsel1 bits refer to the cf1 pin, the termsel2 bits refer to the cf2 pin, and the termsel3 bits refer to the cf3 pin. the termselx[0] bits manage phase a. when set to 1, phase a power is included in the sum of powers at the cfx converter. when cleared to 0, phase a power is not included. the termselx[1] bits manage phase b, and the termselx[2] bits manage phase c. setting all termselx bits to 1 means all 3-phase powers are added at the cfx converter. clearing all termselx bits to 0 means no phase power is added and no cf pulse is generated. second, bits[2:0] (cf1sel[2:0]), bits[5:3] (cf2sel[2:0]), and bits[8:6] (cf3sel[2:0]) in the cfmode register decide what type of power is used at the inputs of the cf1, cf2, and cf3 converters, respectively. table 23 shows the values that cfxsel can have: total active, apparent, fundamental active, or fundamental reactive powers. table 23. cfxsel bits description cfxsel description registers latched when cfxlatch = 1 000 cfx signal proportional to the sum of total phase active powers awatthr, bwatthr, cwatthr 001 reserved 010 cfx signal proportional to the sum of phase apparent powers avahr, bvahr, cvahr 011 cfx signal proportional to the sum of fundamental phase active powers afwatthr, bfwatthr, cfwatthr 100 cfx signal proportional to the sum of fundamental phase reactive powers afvarhr, bfvarhr, cfvarhr 101 to 111 reserved
ade7880 data sheet rev. a | page 66 of 104 by default, the termselx bits are all 1 and the cf1sel bits are 000, the cf2sel bits are 100, and the cf3sel bits are 010. this means that by default, the cf1 digital-to-frequency converter produces signals proportional to the sum of all 3-phase total active powers, cf2 produces signals proportional to fundamental reactive powers, and cf3 produces signals proportional to apparent powers. similar to the energy accumulation process, the energy-to- frequency conversion is accomplished in two stages. the first stage is the same stage illustrated in the energy accumulation sections of active, reactive and apparent powers (see active energy calculation , fundamental reactive energy calculation , apparent energy calculation sections). the second stage consists of the frequency divider by the cfxden 16-bit unsigned registers. the values of cfxden depend on the meter constant (mc), measured in impulses/kwh and how much energy is assigned to one lsb of various energy registers: xwatthr, xfvarhr, and so forth. suppose a derivative of wh [10 n wh] where n is a positive or negative integer, is desired as one lsb of xwatthr register. then, cfxden is as follows: n mc cfxden 10]imp/kwh[ 10 3 = (49) the derivative of wh must be chosen in such a way to obtain a cfxden register content greater than 1. if cfxden = 1, then the cfx pin stays active low for only 1 s. thus, cfxden register should not be set to 1. the frequency converter cannot accommodate fractional results; the result of the division must be rounded to the nearest integer. if cfxden is set equal to 0, then the ade7880 considers it to be equal to 1. the cfx pulse output stays low for 80 ms if the pulse period is larger than 160 ms (6.25 hz). if the pulse period is smaller than 160 ms and cfxden is an even number, the duty cycle of the pulse output is exactly 50%. if the pulse period is smaller than 160 ms and cfxden is an odd number, the duty cycle of the pulse output is (1+1/ cfxden ) 50% internal accumulator threshold 2 7 wthr 34 27 26 0 0 cfxden freq divider revpsumx bit of status0[31:0] cfx pulse output va watt fwatt fvar cfxsel bits in cfmode termselx bits in compmode 2 7 instantaneous phase a active power instantaneous phase b active power instantaneous phase c active power digital signal processor 10193-062 figure 87. energy-to-frequency conversion
data sheet ade7880 rev. a | page 67 of 104 the cfx pulse output is active low and preferably connected to an led, as shown in figure 88 . v dd cfx pin 10193-063 figure 88. cfx pin recommended connection bits[11:9] (cf3dis, cf2dis, and cf1dis) of the cfmode register decide if the frequency converter output is generated at the cf3, cf2, or cf1 pin. when bit cfxdis is set to 1 (the default value), the cfx pin is disabled and the pin stays high. when bit cfxdis is cleared to 0, the corresponding cfx pin output generates an active low signal. bits[16:14] (cf3, cf2, cf1) in the interrupt mask register mask0 manage the cf3, cf2, and cf1 related interrupts. when the cfx bits are set, whenever a high-to-low transition at the corresponding frequency converter output occurs, an interrupt irq0 is triggered and a status bit in the status0 register is set to 1. the interrupt is available even if the cfx output is not enabled by the cfxdis bits in the cfmode register. synchronizing energy registers with cfx outputs the ade7880 contains a feature that allows synchronizing the content of phase energy accumulation registers with the generation of a cfx pulse. when a high-to-low transition at one frequency converter output occurs, the content of all internal phase energy registers that relate to the power being output at cfx pin is latched into hour registers and then resets to 0. see table 23 for the list of registers that are latched based on the cfxsel[2:0] bits in the cfmode register. all 3-phase registers are latched independent of the termselx bits of the compmode register. the process is shown in figure 89 for cf1sel[2:0] = 010 (apparent powers contribute at the cf1 pin) and cfcyc = 2. the cfcyc 8-bit unsigned register contains the number of high to low transitions at the frequency converter output between two consecutive latches. avoid writing a new value into the cfcyc register during a high-to-low transition at any cfx pin. cfcyc = 2 avahr, bvahr, cvahr latched energy registers reset avahr, bvahr, cvahr latched energy registers reset cf1 pulse based on phase a and phase b apparent powers 10193-064 figure 89. synchronizing avahr and bvahr with cf1 bits[14:12] (cf3latch, cf2latch, and cf1latch) of the cfmode register enable this process when set to 1. when cleared to 0, the default state, no latch occurs. the process is available even if the cfx output is not enabled by the cfxdis bits in the cfmode register. energy registers and cf outputs for various accumulation modes bits[1:0] (wattacc[1:0]) in the accmode register deter- mine the accumulation modes of the total and fundamental active powers when signals proportional to the active powers are chosen at the cfx pins (the cfxsel[2:0] bits in the cfmode register equal 000 or 011). they also determine the accumulation modes of the watt-hour energy registers (awatthr, bwatthr, c wat t h r , a f wat t h r , b f wat t h r a n d c f wat t h r ) . when wattacc[1:0] = 00 (the default value), the active powers are sign accumulated in the watt-hour registers and before entering the energy-to-frequency converter. figure 90 shows how signed active power accumulation works. in this mode, the cfx pulses synchronize perfectly with the active energy accumulated in xwatthr registers because the powers are sign accumulated in both data paths. neg pos pos apnoload sign = positive neg no-load threshold active power no-load threshold a ctive energy revapx bit in status0 xwsign bit in phsign 10193-065 figure 90. active power signed accumulation mode when wattacc[1:0] = 01, the active powers are accumulated in positive only mode. when the powers are negative, the watt- hour energy registers are not accumulated. cfx pulses are generated based on signed accumulation mode. in this mode, the cfx pulses do not synchronize perfectly with the active energy accumulated in xwatthr registers because the powers are accumulated differently in each data path. figure 91 shows how positive only active power accumulation works. wattacc[1:0] = 10 setting is reserved and the ade7880 behaves identically to the case when wattacc[1:0] = 00. when wattacc[1:0] = 11, the active powers are accumulated in absolute mode. when the powers are negative, they change sign and accumulate together with the positive power in the watt-hour registers and before entering the energy-to-frequency
ade7880 data sheet rev. a | page 68 of 104 converter. in this mode, the cfx pulses synchronize perfectly with the active energy accumulated in xwatthr registers because the powers are accumulated in the same way in both data paths. figure 92 shows how absolute active power accumulation works. neg pos pos apnoload sign = positive neg no-load threshold active power no-load threshold active energy revapx bit in status0 xwsign bit in phsign 10193-066 figure 91. active power positive only accumulation mode bits[3:2] (varacc[1:0]) in the accmode register determine the accumulation modes of the fundamental reactive powers when signals proportional to the fundamental reactive powers are chosen at the cfx pins (the cfxsel[2:0] bits in the cfmode register equal 100). when varacc[1:0] = 00, the default value, the fundamental reactive powers are sign accumulated in the var-hour energy registers and before entering the energy-to- frequency converter. figure 93 shows how signed fundamental reactive power accumulation works. in this mode, the cfx pulses synchronize perfectly with the fundamental reactive energy accumulated in the xfvarhr registers because the powers are sign accumulated in both data paths. varacc[1:0] = 01 setting is reserved and ade7880 behaves identically to the case when varacc[1:0] = 00. when varacc[1:0] = 10, the fundamental reactive powers are accumulated depending on the sign of the corresponding active power in the var-hour energy registers and before entering the energy-to-frequency converter. if the fundamental active power is positive or considered 0 when lower than the no load threshold, the fundamental reactive power is accumulated as is. if the fundamental active power is negative, the sign of the fundamental reactive power is changed for accumulation. figure 94 shows how the sign adjusted fundamental reactive power accumulation mode works. in this mode, the cfx pulses synchronize perfectly with the fundamental reactive energy accumulated in xfvarhr registers because the powers are accumulated in the same way in both data paths. neg pos pos apnoload sign = positive neg no-load threshold active power no-load threshold a ctive energy revapx bit in status0 xwsign bit in phsign 10193-067 figure 92. active power absolute accumulation mode neg pos pos varnoload sign = positive neg no-load threshold reactive power no-load threshold reactive energy revrpx bit in status0 xvarsign bit in phsign 10193-068 figure 93. fundamental reactive power signed accumulation mode when varacc[1:0] = 11, the fundamental reactive powers are accumulated in absolute mode. when the powers are negative, they change sign and accumulate together with the positive power in the var-hour registers. cfx pulses are generated based on signed accumulation mode. in this mode, the cfx pulses do not synchronize perfectly with the fundamental reactive energy accumulated in x varhr registers because the powers are accumulated differently in each data path. figure 95 shows how absolute fundamental reactive power accumulation works. sign of sum-of-phase powers in the cfx datapath the ade7880 has sign detection circuitry for the sum of phase powers that are used in the cfx data path. as seen in the beginning of the energy-to-frequency conversion section, the energy accumulation in the cfx data path is executed in two stages. every time a sign change is detected in the energy accumulation at the end of the first stage, that is, after the
data sheet ade7880 rev. a | page 69 of 104 energy accumulated into the accumulator reaches one of the wthr, varthr, or vathr thresholds, a dedicated interrupt can be triggered synchronously with the corresponding cfx pulse. the sign of each sum can be read in the phsign register. pos pos varnoload sign = positive neg no-load threshold no-load threshold no-load threshold reactive power active power reactive energy revrpx bit in status0 x varsign bi t in phsign 10193-069 figure 94. fundamental reactive power accumulation in sign adjusted mode neg pos pos varnoload sign = positive neg no-load threshold reactive power no-load threshold reactive energy revapx bit in status0 xvarsign bit in phsign 10193-070 figure 95. fundamental reactive powe r accumulation in absolute mode bit 18, bit 13, and bit 9 (revpsum3, revpsum2, and revpsum1, respectively) of the status0 register are set to 1 when a sign change of the sum of powers in cf3, cf2, or cf1 data paths occurs. to correlate these events with the pulses generated at the cfx pins, after a sign change occurs, bit revpsum3, bit revpsum2, and bit revpsum1 are set in the same moment in which a high-to-low transition at the cf3, cf2, and cf1 pin, respectively, occurs. bit 8, bit 7, and bit 3 (sum3sign, sum2sign, and sum1sign, respectively) of the phsign register are set in the same moment with bit revpsum3, bit revpsum2, and bit evpsum1 and indicate the sign of the sum of phase powers. when cleared to 0, the sum is positive. when set to 1, the sum is negative. interrupts attached to bit 18, bit 13, and bit 9 (revpsum3, revpsum2, and revpsum1, respectively) in the status0 register are enabled by setting bit 18, bit 13, and bit 9 in the mask0 register. if enabled, the irq0 pin is set low, and the status bit is set to 1 whenever a change of sign occurs. to find the phase that triggered the interrupt, the phsign register is read immediately after reading the status0 register. next, the status bit is cleared, and the irq0 pin is set high again by writing to the status0 register with the corresponding bit set to 1. no load condition the no load condition is defined in metering equipment standards as occurring when the voltage is applied to the meter and no cur- rent flows in the current circuit. to eliminate any creep effects in the meter, the ade7880 contains three separate no load detection circuits: one related to the total active power, one related to the fundamental active and reactive powers, and one related to the apparent powers. no load detection based on total active power and apparent power this no load condition uses the total active energy and the apparent energy to trigger this no load condition. the apparent energy is proportional to the rms values of the corresponding phase current and voltage. if neither total active energy nor apparent energy are accumulated for a time indicated in the respective apnoload and vanoload unsigned 16-bit registers, the no load condition is triggered, the total active energy of that phase is not accumulated and no cfx pulses are generated based on the total active energy. the equations used to compute the apnoload and vanoload unsigned 16-bit values are pmax wthry apnoload 17 16 2 2 ?= pmax vathry vanoload 17 16 2 2 ?= (50) where: y is the required no load current threshold computed relative to full scale. for example, if the no load threshold current is set 10,000 times lower than full scale value, then y = 10,000. wthr and vathr represent values stored in the wthr and vathr registers and are used as the thresholds in the first stage energy accumulators for active and apparent energy, respectively (see active energy calculation section). pmax = 27,059,678 = 0x19ce5de, the instantaneous active power computed when the adc inputs are at full scale.
ade7880 data sheet rev. a | page 70 of 104 the vanoload register usually contains the same value as the apnoload register. when apnoload and vanoload are set to 0x0, the no load detection circuit is disabled. if only vanoload is set to 0, then the no load condition is triggered based only on the total active power being lower than apnoload. in the same way, if only apnoload is set to 0x0, the no load condition is triggered based only on the apparent power being lower than vanoload. bit 0 (nload) in the status1 register is set when a no load condition in one of the three phases is triggered. bits[2:0] (nlphase[2:0]) in the phnoload register indicate the state of all phases relative to a no load condition and are set simulta- neously with bit nload in the status1 register. nlphase[0] indicates the state of phase a, nlphase[1] indicates the state of phase b, and nlphase[2] indicates the state of phase c. when bit nlphase[x] is cleared to 0, it means the phase is out of a no load condition. when set to 1, it means the phase is in a no load condition. an interrupt attached to bit 0 (nload) in the status1 register can be enabled by setting bit 0 in the mask1 register. if enabled, the irq1 pin is set to low, and the status bit is set to 1 whenever one of three phases enters or exits this no load condition. to find the phase that triggered the interrupt, the phnoload register is read immediately after reading the status1 register. next, the status bit is cleared, and the irq1 pin is set to high by writing to the status1 register with the corresponding bit set to 1. no load detection based on fundamental active and reactive powers this no load condition is triggered when no less significant bits are accumulated into the fundamental active and reactive energy registers on one phase (xfwatthr and xfvarhr, x = a, b, or c) for a time indicated in the respective apnoload and varnoload unsigned 16-bit registers. in this case, the fundamental active and reactive energies of that phase are not accumulated and no cfx pulses are generated based on these energies. apnoload is the same no load threshold set for the total active powers. the varnoload register usually contains the same value as the apnoload register. if only apnoload is set to 0x0, then the fundamental active power is accumulated without restriction. in the same way, if only varnoload is set to 0x0, the fundamental reactive power is accumulated without restriction. bit 1 (fnload) in the status1 register is set when this no load condition in one of the three phases is triggered. bits[5:3] (fnlphase[2:0]) in the phnoload register indicate the state of all phases relative to a no load condition and are set simultaneously with bit fnload in the status1 register. fnlphase[0] indicates the state of phase a, fnlphase[1] indicates the state of phase b, and fnlphase[2] indicates the state of phase c. when bit fnlphase[x] is cleared to 0, it means the phase is out of the no load condition. when set to 1, it means the phase is in a no load condition. an interrupt attached to the bit 1 (fnload) in the status1 register can be enabled by setting bit 1 in the mask1 register. if enabled, the irq1 pin is set low and the status bit is set to 1 whenever one of three phases enters or exits this no load condition. to find the phase that triggered the interrupt, the phnoload register is read immediately after reading the status1 register. then the status bit is cleared and the irq1 pin is set back high by writing to the status1 register with the corresponding bit set to 1. no load detection based on apparent power this no load condition is triggered when no less significant bits are accumulated into the apparent energy register on one phase (xvahr, x = a, b, or c) for a time indicated by the vanoload unsigned 16-bit register. in this case, the apparent energy of that phase is not accumulated and no cfx pulses are generated based on this energy. the equation used to compute the vanoload unsigned 16-bit value is pmax vathry vanoload 17 16 2 2 ?= (51) where: y is the required no load current threshold computed relative to full scale. for example, if the no load threshold current is set 10,000 times lower than full scale value, then y=10,000. vathr is the vathr register used as the threshold of the first stage energy accumulator (see apparent energy calculation section) pmax = 27,059,678 = 0x19ce5de, the instantaneous apparent power computed when the adc inputs are at full scale. when the vanoload register is set to 0x0, the no load detection circuit is disabled. b it 2 (vanload) in the status1 register is set when this no load condition in one of the three phases is triggered. bits[8:6] (vanlphase[2:0]) in the phnoload register indicate the state of all phases relative to a no load condition and they are set simultaneously with bit vanload in the status1 register: ? bit vanlphase[0] indicates the state of phase a. ? bit vanlphase[1] indicates the state of phase b. ? bit vanlphase[2] indicates the state of phase c. when bit vanlphase[x] is cleared to 0, it means the phase is out of no load condition. when set to 1, it means the phase is in no load condition. an interrupt attached to bit 2 (vanload) in the status1 register is enabled by setting bit 2 in the mask1 register. if enabled, the irq1 pin is set low and the status bit is set to 1 whenever one of three phases enters or exits this no load condition. to find the phase that triggered the interrupt, the phnoload register is read immediately after reading the status1 register. next, the status bit is cleared, and the irq1 pin is set to high by writing to the status1 register with the corresponding bit set to 1.
data sheet ade7880 rev. a | page 71 of 104 checksum register the ade7880 has a checksum 32-bit register, checksum, that ensures the configuration registers maintain their desired value during normal power mode psm0. the registers covered by this register are mask0, mask1, compmode, gain, cfmode, cf1den, cf2den, cf3den, config, mmode, accmode, lcycmode, hsdc_cfg, all registers located in the dsp data memory ram between address 0x4380 and address 0x43be and another eight 8-bit reserved internal registers that always have default values. the ade7880 computes the cyclic redundancy check (crc) based on the ieee802.3 standard. the registers are introduced one-by- one into a linear feedback shift register (lfsr) based generator starting with the least significant bit (as shown in figure 96 ). the 32-bit result is written in the checksum register. after power-up or a hardware/software reset, the crc is computed on the default values of the registers giving a result equal to 0xaffa63b9. figure 97 shows how the lfsr works: the mask0, mask1, compmode, gain, cfmode, cf1den, cf2den, cf3den, config, mmode, accmode, lcycmode, and hsdc_cfg registers, the registers located between address 0x4380, and address 0x43be and the eight 8-bit reserved internal registers form the bits [a 2271 , a 2270 ,, a 0 ] used by lfsr. bit a 0 is the least significant bit of the first register to enter lfsr; bit a 2271 is the most significant bit of the last register to enter lfsr. the formulas that govern lfsr are as follows: ? b i (0) = 1, i = 0, 1, 2, , 31, the initial state of the bits that form the crc. bit b 0 is the least significant bit, and bit b 31 is the most significant. ? g i , i = 0, 1, 2, , 31 are the coefficients of the generating polynomial defined by the ieee802.3 standard as follows: g ( x ) = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 (52) g 0 = g 1 = g 2 = g 4 = g 5 = g 7 = 1 g 8 = g 10 = g 11 = g 12 = g 16 = g 22 = g 26 = 1 (53) all of the other g i coefficients are equal to 0. fb ( j) = a j C 1 xor b 31 ( j ? 1) (54) b 0 ( j) = fb ( j) and g 0 (55) b i (j) = fb ( j) and g i xor b i C 1 ( j C 1), i = 1, 2, 3, ..., 31 (56) equation 54, equation 55, and equation 56 must be repeated for j = 1, 2, , 2272. the value written into the checksum register contains the bit b i (2272) , i = 0, 1, , 31. every time a configuration register of the ade7880 is written or changes value inadvertently, the bit 25 (crc) in status1 register is set to 1 to signal checksum value has changed. if bit 25 (crc) in mask1 register is set to 1, then the irq1 interrupt pin is driven low and the status flag crc in status1 is set to 1. the status bit is cleared and the irq1 pin is set to high by writing to the status1 register with the status bit set to 1. when bit crc in status1 is set to 1 without any register being written, it can be assumed that one of the registers has changed value and therefore, the ade7880 has changed configuration. the recommended response is to initiate a hardware/software reset that sets the values of all registers to the default, including the reserved ones, and then reinitialize the configuration registers. 2 271 0 lfsr generator array of 2272 bits 10193-071 figure 96. checksum register calculation b 0 lfsr fb g 0 g 1 g 2 g 31 b 1 g 3 b 2 b 31 a 1767 , a 1766 ,...., a 2 , a 1 , a 0 10193-072 figure 97. lfsr generator used in checksum register calculation
ade7880 data sheet rev. a | page 72 of 104 interrupts the ade7880 has two interrupt pins, irq0 and irq1 . each of the pins is managed by a 32-bit interrupt mask register, mask0 and mask1, respectively. to enable an interrupt, a bit in the maskx register must be set to 1. to disable it, the bit must be cleared to 0. two 32-bit status registers, status0 and status1, are associated with the interrupts. when an interrupt event occurs in the , the corresponding flag in the interrupt status register is set to a logic 1 (see and ). if the mask bit for this interrupt in the interrupt mask register is logic 1, then the ade7880 table 36 tabl e 3 7 irqx logic output goes active low. the flag bits in the interrupt status register are set irrespective of the state of the mask bits. to determine the source of the interrupt, the mcu should perform a read of the corresponding statusx register and identify which bit is set to 1. to erase the flag in the status register, write back to the statusx register with the flag set to 1. after an interrupt pin goes low, the status register is read and the source of the interrupt is identified. then, the status register is written back without any change to clear the status flag to 0. the irqx pin remains low until the status flag is cancelled. by default, all interrupts are disabled. however, the rstdone interrupt is an exception. this interrupt can never be masked (disabled) and, therefore, bit 15 (rstdone) in the mask1 register does not have any functionality. the irq1 pin always goes low, and bit 15 (rstdone) in the status1 register is set to 1 whenever a power-up or a hardware/software reset process ends. to cancel the status flag, the status1 register has to be written with bit 15 (rstdone) set to 1. c ertain interrupts are used in conjunction with other status registers. the following bits in the mask1 register work in conjunction with the status bits in the phnoload register: ? bit 0 (nload) ? bit 1 (fnload) ? bit 2 (vanload) t he following bits in the mask1 register work with the status bits in the phstatus register: ? bit 16, (sag) ? bit 17 (oi) ? bit 18 (ov) t he following bits in the mask1 register work with the status bits in the ipeak and vpeak registers, respectively: ? bit 23 (pki) ? bit 24 (pkv) t he following bits in the mask0 register work with the status bits in the phsign register: ? bits[6:8] (revapx) ? bits[10:12] (revrpx) ? bit 9, bit 13, and bit 18 (revpsumx) when the statusx register is read and one of these bits is set to 1, the status register associated with the bit is immediately read to identify the phase that triggered the interrupt and only at that time can the statusx register be written back with the bit set to 1. using the interrupts with an mcu figure 98 shows a timing diagram that illustrates a suggested implementation of the ade7880 interrupt management using an mcu. at time t 1 , the irqx pin goes active low indicating that one or more interrupt events have occurred in the , at which point the following steps should be taken: ade7880 1. tie the irqx pin to a negative-edge-triggered external interrupt on the mcu. 2. on detection of the negative edge, configure the mcu to start executing its interrupt service routine (isr). 3. on entering the isr, disable all interrupts using the global interrupt mask bit. at this point, the mcu external interrupt flag can be cleared to capture interrupt events that occur during the current isr. 4. when the mcu interrupt flag is cleared, a read from statusx, the interrupt status register, is carried out. the interrupt status register content is used to determine the source of the interrupt(s) and, hence, the appropriate action to be taken. 5. the same statusx content is written back into the ade7880 to clear the status flag(s) and reset the irqx line to logic high (t 2 ). if a subsequent interrupt event occurs during the isr (t 3 ), that event is recorded by the mcu external interrupt flag being set again. on returning from the isr, the global interrupt mask bit is cleared (same instruction cycle) and the external interrupt flag uses the mcu to jump to its isr once again. this ensures that the mcu does not miss any external interrupts. figure 99 shows a recommended timing diagram when the status bits in the statusx registers work in conjunction with bits in other registers. when the irqx pin goes active low, the statusx register is read, and if one of these bits is 1, a second status register is read immediately to identify the phase that triggered the interrupt. the name, phx, in denotes one of the phstatus, ipeak, vpeak, or phsign registers. then, statusx is written back to clear the status flag(s). figure 99
data sheet ade7880 rev. a | page 73 of 104 jump to isr global interrupt mask clear mcu interrupt flag read statusx jump to isr write back statusx isr action (based on statusx contents) isr return global interrupt mask reset mcu interrupt flag set program sequence t 2 t 1 t 3 irqx 10193-073 figure 98. interrupt management program sequence irqx jump to isr global interrupt mask clear mcu interrupt flag read statusx read phx jump to isr write back statusx isr action (based on statusx contents) isr return global interrupt mask reset mcu interrupt flag set t 2 t 1 t 3 10193-074 figure 99. interrupt management when phstatus, ipeak, vpeak, or phsign registers are involved serial interfaces the ade7880 has three serial port interfaces: one fully licensed i 2 c interface, one serial peripheral interface (spi), and one high speed data capture port (hsdc). as the spi pins are multiplexed with some of the pins of the i 2 c and hsdc ports, the ade7880 accepts two configurations: one using the spi port only and one using the i 2 c port in conjunction with the hsdc port. serial interface choice after reset, the hsdc port is always disabled. choose between the i 2 c and spi ports by manipulating the ss /has pin after power-up or after a hardware reset. if the ss /hsa pin is kept high, then the uses the i 2 c port until a new hardware reset is executed. if the ade7880 ss /hsa pin is toggled high to low three times after power-up or after a hardware reset, the uses the spi port until a new hardware reset is executed. this manipulation of the ade7880 ss /hsa pin can be accomplished in two ways. first, use the ss /hsa pin of the master device (that is, the microcontroller) as a regular i/o pin and toggle it three times. second, execute three spi write operations to a location in the address space that is not allocated to a specific register (for example 0xebff, where eight bit writes can be executed). these writes allow the ade7880 ss /hsa pin to toggle three times. see the section for details on the write protocol involved. spi write operation after the serial port choice is completed, it needs to be locked. consequently, the active port remains in use until a hardware reset is executed in psm0 normal mode or until a power-down. if i 2 c is the active serial port, bit 1 (i2c_lock) of the config2 register must be set to 1 to lock it in. from this moment, the ade7880 ignores spurious toggling of the ss pin and an eventual switch into using the spi port is no longer possible. if the spi is the active serial port, any write to the config2 register locks the port. from this moment, a switch into using the i 2 c port is no longer possible. once locked, the serial port choice is maintained when the changes psmx power modes. ade7880 the functionality of the ade7880 is accessible via several on- chip registers. the contents of these registers can be updated or read using either the i 2 c or spi interfaces. the hsdc port provides the state of up to 16 registers representing instantaneous values of phase voltages and neutral currents, and active, reactive, and apparent powers. communication verification the ade7880 includes a set of three registers that allow any communication via i 2 c or spi to be verified. the last_op (address 0xea01), last_add (address 0xe9fe) and last_rwdata registers record the nature, address and data of the last successful communication respectively. the last_rwdata register has three separate addresses depending on the length of the successful communication. table 24. last_rwdata r l communication type address 8-bit read/write 0xe7fd 16-bit read/write 0xe9ff 24-bit read/write 0xe5ff after each successful communication with the ade7880 , the address of the register that was last accessed is stored in the 16-bit last_add register (address 0xe9fe). this is a read only register that stores the value until the next successful read or write is complete. the last_op register (address 0xea01) stores the nature of the operation. that is, it indicates whether a read or a write was performed. if the last operation is a write, the last_op register stores the value 0xca. if the last operation is a read, the last_op register stores the value 0x35. the last_rwdata register stores the data that was written or read from the register. any unsuccessful read or write operation is not reflected in these registers. when last_op, last_add and last_rwdata registers are read, their values are not stored into themselves.
ade7880 data sheet rev. a | page 74 of 104 i 2 c-compatible interface the ade7880 supports a fully licensed i 2 c interface. the i 2 c interface is implemented as a full hardware slave. sda is the data i/o pin, and scl is the serial clock. these two pins are shared with the mosi and sclk pins of the on-chip spi interface. the maximum serial clock frequency supported by this interface is 400 khz. the two pins used for data transfer, sda and scl, are configured in a wire-anded format that allows arbitration in a multimaster system. the transfer sequence of an i 2 c system consists of a master device initiating a transfer by generating a start condition while the bus is idle. the master transmits the address of the slave device and the direction of the data transfer in the initial address transfer. if the slave acknowledges, the data transfer is initiated. this continues until the master issues a stop condition, and the bus becomes idle. i 2 c write operation the write operation using the i 2 c interface of the ade7880 initiate when the master generates a start condition and consists in one byte representing the address of the ade7880 followed by the 16-bit address of the target register and by the value of the register. the most significant seven bits of the address byte constitute the address of the ade7880 and they are equal to 0111000b. bit 0 of the address byte is a read/ write bit. because this is a write operation, it has to be cleared to 0; therefore, the first byte of the write operation is 0x70. after every byte is received, the generates an acknowledge. as registers can have 8, 16, or 32 bits, after the last bit of the register is transmitted and the acknowledges the transfer, the master generates a stop condition. the addresses and the register content are sent with the most significant bit first. see for details of the i 2 c write operation. ade7880 ade7880 figure 100 ack generated by ade7880 start ack ack ack ack ack ack ack stop s s 0 15 slave address most significant 8 bits of register address less significant 8 bits of register address byte 3 (most significant) of register byte 2 of register byte 1 of register byte 0 (less significant) of register 87 031 2423 1615 8 0 7 1110000 10193-075 figure 100. i 2 c write operation of a 32-bit register
data sheet ade7880 rev. a | page 75 of 104 i 2 c read operation the read operation using the i 2 c interface of the ade7880 is accomplished in two stages. the first stage sets the pointer to the address of the register. the second stage reads the content of the register. as seen in figure 101 , the first stage initiates when the master generates a start condition and consists in one byte representing the address of the ade7880 followed by the 16-bit address of the target register. the ade7880 acknowledges every byte received. the address byte is similar to the address byte of a write operation and is equal to 0x70 (see the i 2 c write operation section for details). after the last byte of the register address has been sent and acknowledged by the ade7880 , the second stage begins with the master generating a new start condition followed by an address byte. the most significant seven bits of this address byte constitute the address of the ade7880 , and they are equal to 0111000b. bit 0 of the address byte is a read/ write bit. because this is a read operation, it must be set to 1; thus, the first byte of the read operation is 0x71. after this byte is received, the generates an acknowledge. then, the sends the value of the register, and after every eight bits are received, the master generates an acknowledge. all the bytes are sent with the most significant bit first. because registers can have 8, 16, or 32 bits, after the last bit of the register is received, the master does not acknowledge the transfer but generates a stop condition. ade7880 ade7880 ack generated by ade7880 acknowledge generated by master star t s0 15 slave address most significant 8 bits of register address less significant 8 bits of register address 87 0 1110000 start stop noack s s 0 slave address byte 3 (most significant) of register byte 2 of register byte 1 of register byte 0 (less signifi cant) of register 31 24 23 16 15 8 0 7 1110001 ack generated by ade7880 ack ack ack ack ack ack ack 10193-076 figure 101. i 2 c read operation of a 32-bit register ack generated by ade7880 acknowledge generated by master star t start noack stop s0 15 slave address most significant 8 bits of register address less significant 8 bits of register address 87 0 1110000 byte 3 (most significant) of register 0 byte 0 (less significant) of register 0 byte 3 (most significant) of register 1 byte 0 (less signifi cant) of register n ack ack ack ack ack ack ack s 0111000 slave address s 31 24 1 70 31 24 70 ack generated by ade7880 10193-077 figure 102. i 2 c read operation of n 32-bit harmonic calculations registers
ade7880 data sheet rev. a | page 76 of 104 i 2 c read operation of harmonic calculations registers the registers containing the harmonic calculation results are located starting at address 0xe880 and are all 32-bit width. they can be read in two ways: one register at a time (see the i 2 c read operation section for details) or multiple consecutive registers at a time in a burst mode. this burst mode is accomplished in two stages. as seen in figure 102 , the first stage sets the pointer to the address of the register and is identical to the first stage executed when only one register is read. the second stage reads the content of the registers. the second stage begins with the master generating a new start condition followed by an address byte equal to the address byte used when one single register is read, 0x71. after this byte is received, the ade7880 generates an acknowledge. then, the ade7880 sends the value of the first register located at the pointer, and after every eight bits are received, the master generates an acknowledge. all the bytes are sent with the most significant bit first. after the bytes of the first register are sent, if the master acknowledges the last byte, the ade7880 increments the pointer by one location to position it at the next register and begins to send it out byte by byte, most significant bit first. if the master acknowledges the last byte, the ade7880 increments the pointer again and begins to send data from the next register. the process continues until the master ceases to generate an acknowledge at the last byte of the register and then generates a stop condition. it is recommended to not allow locations greater then 0xe89f, the last location of the harmonic calculations registers. spi-compatible interface the spi of the ade7880 is always a slave of the communication and consists of four pins (with dual functions): sclk/scl, mosi/sda, miso/hsd, and ss /hsa. the functions used in the spi-compatible interface are sclk, mosi, miso, and ss . the serial clock for a data transfer is applied at the sclk logic input. all data transfer operations synchronize to the serial clock. data shifts into the at the mosi logic input on the falling edge of sclk and the samples it on the rising edge of sclk. data shifts out of the at the miso logic output on a falling edge of sclk and can be sampled by the master device on the raising edge of sclk. the most significant bit of the word is shifted in and out first. the maximum serial clock frequency supported by this interface is 2.5 mhz. miso stays in high impedance when no data is transmitted from the . see for details of the connection between the spi and a master device containing an spi interface. ade7880 ade7880 ade7880 ade7880 figure 103 ade7880 the ss logic input is the chip select input. this input is used when multiple devices share the serial bus. drive the ss input low for the entire data transfer operation. bringing ss high during a data transfer operation aborts the transfer and places the serial bus in a high impedance state. a new transfer can then be initiated by returning the ss logic input to low. however, because aborting a data transfer before completion leaves the accessed register in a state that cannot be guaranteed, every time a register is written, its value should be verified by reading it back. the protocol is similar to the protocol used in i 2 c interface. mosi miso sclk ade7880 mosi miso sck spi device ss ss 10193-078 figure 103. connecting ade7880 spi with an spi device spi read operation the read operation using the spi interface of the ade7880 initiate when the master sets the ss /hsa pin low and begins sending one byte, representing the address of the , on the mosi line. the master sets data on the mosi line starting with the first high-to-low transition of sclk. the spi of the samples data on the low-to-high transitions of sclk. the most significant seven bits of the address byte can have any value, but as a good programming practice, they should be different from 0111000b, the seven bits used in the i 2 c protocol. bit 0 (read/ ade7880 ade7880 write ) of the address byte must be 1 for a read operation. next, the master sends the 16-bit address of the register that is read. after the receives the last bit of address of the register on a low-to-high transition of sclk, it begins to transmit its contents on the miso line when the next sclk high-to-low transition occurs; thus, the master can sample the data on a low-to-high sclk transition. after the master receives the last bit, it sets the ade7880 ss and sclk lines high and the communication ends. the data lines, mosi and miso, go into a high impedance state. see for details of the spi read operation. figure 104
data sheet ade7880 rev. a | page 77 of 104 1 0 15 14 scl k mosi miso 10 31 30 1 0 0 0 0 000 register value register address ss 10193-079 figure 104. spi read operation of a 32-bit register 0 s clk mosi miso 0 0 0 0001 ss register address register 0 value 31 0 register n value 31 0 10193-080 figure 105. spi read operation of n 32-bit harmonic calculations registers spi read operation of harmonic calculations registers the registers containing the harmonic calculation results are located starting at address 0xe880 and are all 32-bit width. they can be read in two ways: one register at a time (see the spi read operation section for details) or multiple consecutive registers at a time in a burst mode. the burst mode initiates when the master sets the ss /hsa pin low and begins sending one byte, representing the address of the , on the mosi line. the address is the same address byte used for reading only one register. the master sets data on the mosi line starting with the first high-to-low transition of sclk. the spi of the samples data on the low-to-high transitions of sclk. next, the master sends the 16-bit address of the first harmonic calculations register that is read. after the receives the last bit of the address of the register on a low-to- high transition of sclk, it begins to transmit its contents on the miso line when the next sclk high-to-low transition occurs; thus, the master can sample the data on a low-to-high sclk transition. after the master receives the last bit of the first register, the sends the harmonic calculations register placed at the next location and so forth until the master sets the ade7880 ade7880 ade7880 ade7880 ss and sclk lines high and the communication ends. the data lines, mosi and miso, go into a high impedance state. see for details of the spi read operation of harmonic calculations registers. figure 105 spi write operation the write operation using the spi interface of the ade7880 initiates when the master sets the ss /hsa pin low and begins sending one byte representing the address of the on the mosi line. the master sets data on the mosi line starting with the first high-to-low transition of sclk. the spi of the samples data on the low-to-high transitions of sclk. the most significant seven bits of the address byte can have any value, but as a good programming practice, they should be different from 0111000b, the seven bits used in the i 2 c protocol. bit 0 (read/ ade7880 ade7880 write ) of the address byte must be 0 for a write operation. next, the master sends both the 16-bit address of the register that is written and the 32-, 16-, or 8-bit value of that register without losing any sclk cycle. after the last bit is transmitted, the master sets the ss and sclk lines high at the end of the sclk cycle and the communication ends. the data lines, mosi and miso, go into a high impedance state. see for details of the spi write operation. figure 106
ade7880 data sheet rev. a | page 78 of 104 0 15 14 sclk mosi 103130 10 0 0 0 0000 register address register value ss 10193-081 figure 106. spi write operation of a 32-bit register hsdc interface the high speed data capture (hsdc) interface is disabled after default. it can be used only if the ade7880 is configured with an i 2 c interface. the spi interface of ade7880 cannot be used at the same time with hsdc. bit 6 (hsdcen) in the config register activates hsdc when set to 1. if bit hsdcen is cleared to 0, the default value, the hsdc interface is disabled. setting bit hsdcen to 1 when spi is in use does not have any effect. hsdc is an interface for sending to an external device (usually a microprocessor or a dsp) up to sixteen 32-bit words. the words represent the instantaneous values of the phase currents and voltages, neutral current, and active, reactive, and apparent powers. the registers being transmitted include iawv, vawv, ibwv, vbwv, icwv, vcwv, ava, inwv, bva, cva, awatt, bwatt, cwatt, a f va r , b f va r , a n d c f va r . a l l a r e 2 4 - b i t r e g i s t e r s t h a t a r e sign extended to 32-bits (see figure 44 for details). hsdc can be interfaced with spi or similar interfaces. hsdc is always a master of the communication and consists of three pins: hsa, hsd, and hsclk. hsa represents the select signal. it stays active low or high when a word is transmitted and it is usually connected to the select pin of the slave. hsd sends data to the slave and it is usually connected to the data input pin of the slave. hsclk is the serial clock line that is generated by the ade7880 and it is usually connected to the serial clock input of the slave. figure 107 shows the connections between the ade7880 hsdc and slave devices containing an spi interface. ade7880 hsd miso hsclk sck hsa ss spi device 10193-082 figure 107. connecting the ade7880 hsdc with an spi the hsdc communication is managed by the hsdc_cfg register (see table 52 ). it is recommended to set the hsdc_cfg register to the desired value before enabling the port using bit 6 (hsdcen) in the config register. in this way, the state of various pins belonging to the hsdc port do not take levels incon- sistent with the desired hsdc behavior. after a hardware reset or after power-up, the miso/hsd and ss /hsa pins are set high. bit 0 (hclk) in the hsdc_cfg register determines the serial clock frequency of the hsdc communication. when hclk is 0 (the default value), the clock frequency is 8 mhz. when hclk is 1, the clock frequency is 4 mhz. a bit of data is transmitted for every hsclk high-to-low transition. the slave device that receives data from hsdc samples the hsd line on the low-to- high transition of hsclk. the words can be transmitted as 32-bit packages or as 8-bit packages. when bit 1 (hsize) in the hsdc_cfg register is 0 (the default value), the words are transmitted as 32-bit packages. when bit hsize is 1, the registers are transmitted as 8-bit packages. the hsdc interface transmits the words msb first. bit 2 (hgap) introduces a gap of seven hsclk cycles between packages when bit 2 (hgap) is set to 1. when bit hgap is cleared to 0 (the default value), no gap is introduced between packages and the communication time is shortest. in this case, hsize does not have any influence on the communication and a data bit is placed on the hsd line with every hsclk high-to- low transition. bits[4:3] (hxfer[1:0]) decide how many words are transmitted. when hxfer[1:0] is 00, the default value, then all 16 words are transmitted. when hxfer[1:0] is 01, only the words representing the instantaneous values of phase and neutral currents and phase voltages are transmitted in the following order: iawv, vawv, ibwv, vbwv, icwv, vcwv, and one 32-bit word that is always equal to inwv. when hxfer[1:0] is 10, only the instantaneous values of phase powers are transmitted in the following order: ava, bva, cva, awatt, bwatt, cwatt, afvar, bfvar, and cfvar. the value, 11, for hxfer[1:0] is reserved and writing it is equivalent to writing 00, the default value. bit 5 (hsapol) determines the polarity of hsa function of the ss /hsa pin during communication. when hsapol is 0 (the default value), hsa is active low during the communication. this means that hsa stays high when no communication is in progress. when a communication is executed, hsa is low when the 32-bit or 8-bit packages are transferred, and it is high during the gaps. when hsapol is 1, the hsa function of the ss /hsa pin is active high during the communication. this means that hsa stays low when no communication is in progress. when a communication is executed, hsa is high when the 32-bit or 8-bit packages are transferred, and it is low during the gaps. bits[7:6] of the hsdc_cfg register are reserved. any value written into these bits does not have any consequence on hsdc behavior.
data sheet ade7880 rev. a | page 79 of 104 figure 108 shows the hsdc transfer protocol for hgap = 0, hxfer[1:0] = 00 and hsapol = 0. note that the hsdc interface sets a data bit on the hsd line every hsclk high-to- low transition and the value of bit hsize is irrelevant. figure 109 shows the hsdc transfer protocol for hsize = 0, hgap = 1, hxfer[1:0] = 00, and hsapol = 0. note that the hsdc interface introduces a seven-hsclk cycles gap between every 32-bit word. figure 110 shows the hsdc transfer protocol for hsize = 1, hgap = 1, hxfer[1:0] = 00, and hsapol = 0. note that the hsdc interface introduces a seven-hsclk cycles gap between every 8-bit word. see table 52 for the hsdc_cfg register and descriptions for the hclk, hsize, hgap, hxfer[1:0], and hsapol bits. table 25 lists the time it takes to execute an hsdc data transfer for all hsdc_cfg register settings. for some settings, the transfer time is less than 125 s (8 khz), the waveform sample registers update rate. this means the hsdc port transmits data every sampling cycle. for settings in which the transfer time is greater than 125 s, the hsdc port transmits data only in the first of two consecutive 8 khz sampling cycles. this means it transmits registers at an effective rate of 4 khz. table 25. communication times for various hsdc settings hxfer[1:0] hgap hsize 1 hclk communication time (s) 00 0 n/a 0 64 00 0 n/a 1 128 00 1 0 0 77.125 00 1 0 1 154.25 00 1 1 0 119.25 00 1 1 1 238.25 01 0 n/a 0 28 01 0 n/a 1 56 01 1 0 0 33.25 01 1 0 1 66.5 01 1 1 0 51.625 01 1 1 1 103.25 10 0 n/a 0 36 10 0 n/a 1 72 10 1 0 0 43 10 1 0 1 86 10 1 1 0 66.625 10 1 1 1 133.25 1 n/a means not applicable. hsclk hsd hsa iavw (32-bit) 31 0 vawv (32-bit) 31 0 ibwv (32-bit) 31 0 cfvar (32-bit) 31 0 10193-083 figure 108. hsdc communication for hgap = 0, hxfer[1:0] = 00, and hsapol = 0; hsize is irrelevant
ade7880 data sheet rev. a | page 80 of 104 hsclk hsdat a hsa iavw (32-bit) 31 0 vawv (32-bit) 31 0 ibwv (32-bit) 31 0 cfvar (32-bit) 31 0 7 hclk cycles 7 hclk cycles 10193-084 figure 109. hsdc communication for hsize = 0, hgap = 1, hxfer[1:0] = 00, and hsapol = 0 hsclk hsdat a hsa iavw (byte 3) 31 24 iavw (byte 2) 23 16 iavw (byte 1) 15 8 cfvar (byte 0) 70 7 hclk cycles 7 hclk cycles 10193-085 figure 110. hsdc communication for hsize = 1, hgap = 1, hxfer[1:0] = 00, and hsapol = 0 ade7880 quick setup as energy meter an energy meter is usually characterized by the nominal current i n , nominal voltage v n , nominal frequency f n , and the meter constant mc. t o quick ly s et up t he ade7880 , execute the following steps: 1. select the pga gains in the phase currents, voltages and neutral current channels: bits[2:0] (pga1), bits[5:3] (pga2) and bits[8:6] (pga3) in the gain register. 2. if rogowski coils are used, enable the digital integrators in the phase or neutral currents channels: bit 0 (inten) in config register and bit 3 (ininten) in config3 register. 3. if f n = 60 hz, set bit 14 (selfreq) to 1 in the compmode register. 4. initialize cf1den, cf2den, and cf3den registers based in equation 49. 5. initialize wthr, varthr, vathr, vlevel and vnom registers based equation 26, equation 37, equation 44, equation 22, and equation 42, respectively. 6. enable the data memory ram protection, by writing 0xad to an internal 8-bit register located at address 0xe7fe, followed by a write of 0x80 to an internal 8-bit register located at address 0xe7e3. 7. start the dsp by setting run = 1. for a quick setup of the ade7880 harmonic calculations, see the recommended approach to managing harmonic calculations section. ade7880 evaluation board an evaluation board built upon the ade7880 configuration is available. visit www.analog.com/ade7880 for details. die version the register named version identifies the version of the die. it is an 8-bit, read-only register located at address 0xe707.
data sheet ade7880 rev. a | page 81 of 104 silicon anomaly this anomaly list describes the known issues with the ade7880 silicon identified by the version register (address 0xe707) being equal to 1. analog devices, inc., is committed, through future silicon revisions, to continuously improve silicon functionality. analog dev ices tries to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommen ded workarounds outlined here. ade7880 functionality issues silicon revision identifier chip marking silicon status anomaly sheet no. of reported issues version = 1 ADE7880ACPZ preliminary rev. a 4 (er001, er002, er003, er004) functionality issues table 26. last_add register shows wrong valu e for harmonic calculations registers in spi mode [er001, version = 1 silicon] background when any ade7880 register is read using spi or i 2 c communication, the address is stored in the last_add register issue when the harmonic calculation registers located between address 0xe880 and address 0xe89f are read using spi communication, the last_add register contains the address of th e register incremented by 1. the issue is not present if the i 2 c communication is used. workaround if the last_add register is read after one of the registers located between address 0xe880 and address 0xe89f was read using spi communication, subtract 1 from it to recover the right address. related issues none. table 27. to obtain best accuracy performance, internal setting must be changed [er002, version = 1 silicon] background internal default settings provide best accuracy performance for ade7880 . issue it was found that if a different setting is us ed, the accuracy performance can be improved. workaround to enable a new setting for this internal regi ster, execute three consecutive write operations: the first write operation is to an 8-bit lo cation: 0xad is written to address 0xe7fe. the second write operation is to a 16-bit location: 0x3bd is written to address 0xe90c. the third write operation is to an 8-bit lo cation: 0x00 is written to address 0xe7ef. the write operations must be executed consecutively wi thout any other read/write operation in between. as a verification that the value was captured correctly, a simple 16-bit read of addre ss 0xe90c should show the 0x3bd value. related issues none. table 28. high-pass filter cannot be disabled in phas e c voltage data path [er003, version = 1 silicon] background when bit 0 (hpfen) of the config3 register is 0, all high-p ass filters (hpf) in the phase and neutral currents and phase voltages data paths are disabled (see the ade7880 data sheet for more information about the current channel hpf and the voltage channel hpf). issue the hpf in the phase c voltage data path remains enabled independent of the state of bit hpfen. workaround there is no workaround. related issues none.
ade7880 data sheet rev. a | page 82 of 104 table 29. no load condition does not function as defined [er004, version = 1 silicon] background total active power no load uses the total active energy and the apparent energy to trigger the no load condition. if neither total active energy nor apparent energy are accumu lated for a time indicated in the respective apnoload and vanoload unsigned, 16-bit registers, the no load condition is triggered, the total active energy of that phase is not accumulated and no cf pulses are generated based on the total active energy. fundamental active and reactive powers no load uses the fund amental active and reactive energies to trigger the no load condition. if neither the fundamental active energy nor th e fundamental reactive energy are accumulated for a time indicated in the respective apnoload and varnoload unsigned 16-bit registers, the no load condition is triggered, the fundamental active and reactive energies of that phase are not accumulated, and no cf pulses are generated based on the fundamental active and reactive energies. issue when the total active energy on phase x (x = a, b, or c) is lower than apnoload and the apparent energy is above vanoload, the no load condition should not be triggered. it was observed that although cf pulses continue to be generated, the bit 0 (nload) and bits[2:0] (nlphase) in st atus1 and phnoload registers continue to be cleared to 0 indicating an out of no load condition, the xwatthr register stops accumulating energy. it was observed that the fundamental active energy no load functions independently of th e fundamental reactive energy no load. if, for example, the fundamental active energy is below apnoload and the fundamental reactive energy is above varnoload, both energies should continue to accumulate because the phase is out of no load condition. instead, the cf pulses, based on the phase fundamental active energy, are not generated and the fwatthr registers are blocked, while the cf pulses, based on the fundamental reactive ener gy, are generated. thus, the fvarhr registers continue to accumulate and the bit 1 (fnload) in the status1 register and bits[5:3] (fnlphase) in the phnoload register are cleared to 0. workaround because both no load conditions use th e apnoload threshold, a workaround for both issues is presented as follows: ? clear apnoload and varnoload to 0. ? set vanoload at desired value. when the phase x (x = a, b, or c) apparent energy become s smaller then vanoload, the bit 2 (vanload) in status1 is set to 1, together with one of the bits[2:0] (vanlphase) in phnoload. then, set apnoload and varnoload equal to vanoload. the phase x (x = a, b, or c) total active energy enters no load condition. ? cf pulses stop. ? bit 0 (nload) in the status1 register is set to 1. ? one of the bits[2:0], (nlphase[2:0]), in the phnoload register is set to 1. ? the xwatthr register stops accumulating energy. the phase x (x = a, b, or c) fundamental active and reactive energies enter no load condition. ? cf pulses stop. ? bit 1 (fnload) in the status1 register is set to 1. ? one of the bits[5:3], (fnlphase[2:0]), in the phnoload register is set to 1. ? the xfwatthr and xvarhr registers stop accumulating energy. related issues none. section 1. ade7880 functionality issues reference number description status er001 the last_add register shows the wrong value for the ha rmonic calculations registers in spi mode. identified er002 to obtain the best accuracy performance, the internal setting must be changed. identified er003 the high-pass filter cannot be disabled in the phase c voltage data path identified er004 the no load condition does not function as defined. identified
data sheet ade7880 rev. a | page 83 of 104 registers list table 30. registers located in dsp data memory ram address register name r/w 1 bit length bit length during communication 2 type 3 default value description 0x4380 aigain r/w 24 32 zpse s 0x000000 phase a current gain adjust. 0x4381 avgain r/w 24 32 zpse s 0x000000 phase a voltage gain adjust. 0x4382 bigain r/w 24 32 zpse s 0x000000 phase b current gain adjust. 0x4383 bvgain r/w 24 32 zpse s 0x000000 phase b voltage gain adjust. 0x4384 cigain r/w 24 32 zpse s 0x000000 phase c current gain adjust. 0x4385 cvgain r/w 24 32 zpse s 0x000000 phase c voltage gain adjust. 0x4386 nigain r/w 24 32 zpse s 0x000000 neutral current gain adjust. 0x4387 reserved r/w 24 32 zpse s 0x000000 this lo cation should not be written for proper operation. 0x4388 dicoeff r/w 24 32 zpse s 0x0000000 register used in the digital integrator algorithm. if the integrator is turned on, it must be set at 0xff8000. in practice, it is transmitted as 0xfff8000. 0x4389 apgain r/w 24 32 zpse s 0x000000 phase a power gain adjust. 0x438a awattos r/w 24 32 zpse s 0x000000 phase a total active power offset adjust. 0x438b bpgain r/w 24 32 zpse s 0x000000 phase b power gain adjust. 0x438c bwattos r/w 24 32 zpse s 0x000000 phase b total active power offset adjust. 0x438d cpgain r/w 24 32 zpse s 0x000000 phase c power gain adjust. 0x438e cwattos r/w 24 32 zpse s 0x000000 phase c total active power offset adjust. 0x438f airmsos r/w 24 32 zpse s 0x000000 phase a current rms offset. 0x4390 avrmsos r/w 24 32 zpse s 0x000000 phase a voltage rms offset. 0x4391 birmsos r/w 24 32 zpse s 0x000000 phase b current rms offset. 0x4392 bvrmsos r/w 24 32 zpse s 0x000000 phase b voltage rms offset. 0x4393 cirmsos r/w 24 32 zpse s 0x000000 phase c current rms offset. 0x4394 cvrmsos r/w 24 32 zpse s 0x000000 phase c voltage rms offset. 0x4395 nirmsos r/w 24 32 zpse s 0x000000 neutral current rms offset. 0x4396- 0x4397 reserved n/a n/a n/a n/a 0x000000 these memo ry locations should not be written for proper operation. 0x4398 hpgain r/w 24 32 zpse s 0x000000 harmonic powers gain adjust. 0x4399 isumlvl r/w 24 32 zpse s 0x000000 threshold used in comparison between the sum of phase currents and the neutral current. 0x439a- 0x439e reserved n/a n/a n/a n/a 0x000000 these memo ry locations should not be written for proper operation. 0x439f vlevel r/w 24 32 zpse s 0x000000 register used in the algorithm that computes the fundamental active and reactive powers. 0x43a0- 0x43a1 reserved n/a n/a n/a n/a 0x000000 these memo ry locations should not be written for proper operation. 0x43a2 afwattos r/w 24 32 zpse s 0x000000 phase a fundamental active power offset adjust. 0x43a3 bfwattos r/w 24 32 zpse s 0x000000 phase b fundamental active power offset adjust. 0x43a4 cfwattos r/w 24 32 zpse s 0x000000 phas e c fundamental active power offset adjust. 0x43a5 afvaros r/w 24 32 zpse s 0x000000 phase a fundamental reactive power offset adjust. 0x43a6 bfvaros r/w 24 32 zpse s 0x000000 phase b fundamental reactive power offset adjust. 0x43a7 cfvaros r/w 24 32 zpse s 0x000000 phase c fundamental reactive power offset adjust. 0x43a8 afirmsos r/w 24 32 zpse s 0x000000 phase a fundamental current rms offset. 0x43a9 bfirmsos r/w 24 32 zpse s 0x000000 phase b fundamental current rms offset. 0x43aa cfirmsos r/w 24 32 zpse s 0x000000 phase c fundamental current rms offset. 0x43ab afvrmsos r/w 24 32 zpse s 0x000000 phase a fundamental voltage rms offset. 0x43ac bfvrmsos r/w 24 32 zpse s 0x000000 phase b fundamental voltage rms offset. 0x43ad cfvrmsos r/w 24 32 zpse s 0x000000 phase c fundamental voltage rms offset. 0x43ae hxwattos r/w 24 32 zpse s 0x000000 active power offset adjust on harmonic x (see harmonics calculations section for details). 0x43af hywattos r/w 24 32 zpse s 0x000000 aactive power offset adjust on harmonic y (see harmonics calculations section for details).
ade7880 data sheet rev. a | page 84 of 104 address register name r/w 1 bit length bit length during communication 2 type 3 default value description 0x43b0 hzwattos r/w 24 32 zpse s 0x000000 active power offset adjust on harmonic z (see harmonics calculations section for details). 0x43b1 hxvaros r/w 24 32 zpse s 0x000000 aact ive power offset adjust on harmonic x (see harmonics calculations section for details). 0x43b2 hyvaros r/w 24 32 zpse s 0x000000 active power offset adjust on harmonic y (see harmonics calculations section for details). 0x43b3 hzvaros r/w 24 32 zpse s 0x000000 aact ive power offset adjust on harmonic z (see harmonics calculations section for details). 0x43b4 hxirmsos r/w 24 32 zpse s 0x000000 current rms offset on harmonic x (see harmonics calculations section for details). 0x43b5 hyirmsos r/w 24 32 zpse s 0x000000 current rms offset on harmonic y (see harmonics calculations section for details). 0x43b6 hzirmsos r/w 24 32 zpse s 0x000000 current rms offset on harmonic z (see harmonics calculations section for details). 0x43b7 hxvrmsos r/w 24 32 zpse s 0x00000 0 voltage rms offset on harmonic x (see harmonics calculations section for details). 0x43b8 hyvrmsos r/w 24 32 zpse s 0x00000 0 voltage rms offset on harmonic y (see harmonics calculations section for details). 0x43b9 hzvrmsos r/w 24 32 zpse s 0x00000 0 voltage rms offset on harmonic z (see harmonics calculations section for details). 0x43ba to 0x43bf reserved n/a n/a n/a n/a 0x000000 these memo ry locations should not be written for proper operation. 0x43c0 airms r 24 32 zp s n/a phase a current rms value. 0x43c1 avrms r 24 32 zp s n/a phase a voltage rms value. 0x43c2 birms r 24 32 zp s n/a phase b current rms value. 0x43c3 bvrms r 24 32 zp s n/a phase b voltage rms value. 0x43c4 cirms r 24 32 zp s n/a phase c current rms value. 0x43c5 cvrms r 24 32 zp s n/a phase c voltage rms value. 0x43c6 nirms r 24 32 zp s n/a neutral current rms value. 0x43c7 isum r 24 32 zp s n/a sum of iawv, ibwv and icwv registers. 0x43c8 to 0x43ff reserved n/a n/a n/a n/a n/a these memory locations should not be written for proper operation. 1 r is read, and w is write. 2 32 zpse = 24-bit signed register that is transmitted as a 32-bit word with four msbs padded with 0s and sign extended to 28 bi ts. whereas 32 zp = 28- bit or 24-bit signed or unsigned register that is transmitted as a 32-bit word with four or eight msbs, respectively, padded with 0s. 3 u is unsigned register, and s is signed register in twos complement format. table 31. internal dsp memory ram registers address register name r/w 1 bit length bit length during communication type 2 default value description 0xe203 reserved r/w 16 16 u 0x0000 this memory location should not be written for proper operation. 0xe228 run r/w 16 16 u 0x0000 run register starts and stops the dsp. see the digital signal processor section for more details. 1 r is read, and w is write. 2 u is unsigned register, and s is signed register in twos complement format.
data sheet ade7880 rev. a | page 85 of 104 table 32. billable registers address register name r/w 1 , 2 bit length 2 bit length during communication 2 type 2 , 3 default value description 0xe400 awatthr r 32 32 s 0x00000000 phase a total active energy accumulation. 0xe401 bwatthr r 32 32 s 0x00000000 phase b to tal active energy accumulation. 0xe402 cwatthr r 32 32 s 0x00000000 phase c total active energy accumulation. 0xe403 afwatthr r 32 32 s 0x00000000 phase a fundamental active energy accumulation. 0xe404 bfwatthr r 32 32 s 0x00000000 phase b fundamental active energy accumulation. 0xe405 cfwatthr r 32 32 s 0x00000000 phase c fundamental active energy accumulation. 0xe406 to 0xe408 reserved r 32 32 s 0x00000000 0xe409 afvarhr r 32 32 s 0x00000000 phase a fundamental reactive energy accumulation. 0xe40a bfvarhr r 32 32 s 0x00000000 phase b fundamental reactive energy accumulation. 0xe40b cfvarhr r 32 32 s 0x00000000 phase c fundamental reactive energy accumulation. 0xe40c avahr r 32 32 s 0x00000000 phase a apparent energy accumulation. 0xe40d bvahr r 32 32 s 0x00000000 phase b apparent energy accumulation. 0xe40e cvahr r 32 32 s 0x00000000 phase c apparent energy accumulation. 1 r is read, and w is write. 2 n/a is not applicable. 3 u is unsigned register, and s is signed register in twos complement format. table 33. configuration and power quality registers address register name r/w 1 bit length bit length during communication 2 type 3 default value 4 description 0xe500 ipeak r 32 32 u n/a current peak register. see figure 58 and table 34 for details about its composition. 0xe501 vpeak r 32 32 u n/a voltage peak register. see figure 58 and table 35 for details about its composition. 0xe502 status0 r/w 32 32 u n/a interrupt status register 0. see table 36 . 0xe503 status1 r/w 32 32 u n/a inte rrupt status register 1. see table 37 . 0xe504 aimav r 20 32 zp u n/a phase a current mean absolute value computed during psm0 and psm1 modes. 0xe505 bimav r 20 32 zp u n/a phase b current mean absolute value computed during psm0 and psm1 modes. 0xe506 cimav r 20 32 zp u n/a phase c current mean absolute value computed during psm0 and psm1 modes. 0xe507 oilvl r/w 24 32 zp u 0xffffff overcurrent threshold. 0xe508 ovlvl r/w 24 32 zp u 0xffffff overvoltage threshold. 0xe509 saglvl r/w 24 32 zp u 0x000000 voltage sag level threshold. 0xe50a mask0 r/w 32 32 u 0x00000000 interrupt enable register 0. see table 38 . 0xe50b mask1 r/w 32 32 u 0x00000000 interrupt enable register 1. see table 39 . 0xe50c iawv r 24 32 se s n/a instantaneous value of phase a current. 0xe50d ibwv r 24 32 se s n/a instantaneous value of phase b current. 0xe50e icwv r 24 32 se s n/a instantaneous value of phase c current.
ade7880 data sheet rev. a | page 86 of 104 address register name r/w 1 bit length bit length during communication 2 type 3 default value 4 description 0xe50f inwv r 24 32 se s n/a instantaneous value of neutral current. 0xe510 vawv r 24 32 se s n/a instantaneous value of phase a voltage. 0xe511 vbwv r 24 32 se s n/a instantaneous value of phase b voltage. 0xe512 vcwv r 24 32 se s n/a instantaneous value of phase c voltage. 0xe513 awatt r 24 32 se s n/a instantaneous value of phase a total active power. 0xe514 bwatt r 24 32 se s n/a instantaneous value of phase b total active power. 0xe515 cwatt r 24 32 se s n/a instantaneous value of phase c total active power. 0xe516 to 0xe518 reserved r 24 32 se s 0x000000 0xe519 ava r 24 32 se s n/a instantaneous value of phase a apparent power. 0xe51a bva r 24 32 se s n/a instantaneous value of phase b apparent power. 0xe51b cva r 24 32 se s n/a instantaneous value of phase c apparent power. 0xe51f checksum r 32 32 u 0xaffa63b9 checksum verification. see the checksum register section for details. 0xe520 vnom r/w 24 32 zp s 0x000000 nominal phase voltage rms used in the alternative computation of the apparent power. 0xe521 to 0xe5fe reserved these addresses should not be written for proper operation. 0xe5ff last_rwdata32 r 32 32 u n/a contains the data from the last successful 32-bit register communication. 0xe600 phstatus r 16 16 u n/a phase peak register. see table 40 . 0xe601 angle0 r 16 16 u n/a time delay 0. see the time interval between phases section for details. 0xe602 angle1 r 16 16 u n/a time delay 1. see the time interval between phases section for details. 0xe603 angle2 r 16 16 u n/a time delay 2. see the time interval between phases section for details. 0xe604 to 0xe607 reserved these address should not be written for proper operation. 0xe608 phnoload r 16 16 u n/a phase no load register. see table 41 . 0xe609 to 0xe60b reserved these address should not be written for proper operation. 0xe60c linecyc r/w 16 16 u 0xffff line cycle accumulation mode count. 0xe60d zxtout r/w 16 16 u 0xffff zero-crossing timeout count. 0xe60e compmode r/w 16 16 u 0x01ff computation-mode register. see table 42 . 0xe60f gain r/w 16 16 u 0x0000 pga gains at adc inputs. see table 43 . 0xe610 cfmode r/w 16 16 u 0x0ea0 cfx configuration register. see table 44 . 0xe611 cf1den r/w 16 16 u 0x0000 cf1 denominator. 0xe612 cf2den r/w 16 16 u 0x0000 cf2 denominator. 0xe613 cf3den r/w 16 16 u 0x0000 cf3 denominator. 0xe614 aphcal r/w 10 16 zp u 0x0000 phase calibration of phase a. see table 45 . 0xe615 bphcal r/w 10 16 zp u 0x0000 phase calibration of phase b. see table 45 . 0xe616 cphcal r/w 10 16 zp u 0x0000 phase calibration phase of c. see table 45 . 0xe617 phsign r 16 16 u n/a power sign register. see table 46 . 0xe618 config r/w 16 16 u 0x0002 ade7880 configuration register. see table 47 . 0xe700 mmode r/w 8 8 u 0x1c measurement mode register. see table 48 . 0xe701 accmode r/w 8 8 u 0x80 accumulation mode register.
data sheet ade7880 rev. a | page 87 of 104 address register name r/w 1 bit length bit length during communication 2 type 3 default value 4 description see table 49 . 0xe702 lcycmode r/w 8 8 u 0x78 line accumulation mode behavior. see table 51 . 0xe703 peakcyc r/w 8 8 u 0x00 peak detection half line cycles. 0xe704 sagcyc r/w 8 8 u 0x00 sag detection half line cycles. 0xe705 cfcyc r/w 8 8 u 0x01 number of cf pulses between two consecutive energy latches. see the synchronizing energy registers with cfx outputs section. 0xe706 hsdc_cfg r/w 8 8 u 0x00 hsdc configuration register. see table 52 . 0xe707 version r 8 8 u version of die. 0xe7fd last_rwdata8 r 8 8 u n/a contains the data from the last successful 8-bit register communication. 0xe880 fvrms r 24 32 s n/a the rms value of the fundamental component of the phase voltage. 0xe881 firms r 24 32 s n/a the rms value of the fundamental component of the phase current 0xe882 fwatt r 24 32 s n/a the active power of the fundamental component. 0xe883 fvar r 24 32 s n/a the reactive power of the fundamental component. 0xe884 fva r 24 32 s n/a the apparent power of the fundamental component. 0xe885 fpf r 24 32 s n/a the power factor of the fundamental component. 0xe886 vthd r 24 32 s n/a total harmonic distortion of the phase voltage. 0xe887 ithd r 24 32 s n/a total harmonic distortion of the phase current. 0xe888 hxvrms r 24 32 s n/a the rms value of the phase voltage harmonic x. 0xe889 hxirms r 24 32 s n/a the rms value of the phase current harmonic x. 0xe88a hxwatt r 24 32 s n/a the active power of the harmonic x. 0xe88b hxvar r 24 32 s n/a the reactive power of the harmonic x. 0xe88c hxva r 24 32 s n/a the apparent power of the harmonic x. 0xe88d hxpf r 24 32 s n/a the power factor of the harmonic x. 0xe88e hxvhd r 24 32 s n/a harmonic distortion of the phase voltage harmonic x relative to the fundamental. 0xe88f hxihd r 24 32 s n/a harmonic distortion of the phase current harmonic x relative to the fundamental. 0xe890 hyvrms r 24 32 s n/a the rms value of the phase voltage harmonic y. 0xe891 hyirms r 24 32 s n/a the rms value of the phase current harmonic y. 0xe892 hywatt r 24 32 s n/a the active power of the harmonic y. 0xe893 hyvar r 24 32 s n/a the reactive power of the harmonic y. 0xe894 hyva r 24 32 s n/a the apparent power of the harmonic y. 0xe895 hypf r 24 32 s n/a the power factor of the harmonic y. 0xe896 hyvhd r 24 32 s n/a harmonic distortion of the phase voltage harmonic y relative to the fundamental. 0xe897 hyihd r 24 32 s n/a harmonic distortion of the phase
ade7880 data sheet rev. a | page 88 of 104 address register name r/w 1 bit length bit length during communication 2 type 3 default value 4 description current harmonic y relative to the fundamental. 0xe898 hzvrms r 24 32 s n/a the rms value of the phase voltage harmonic z. 0xe899 hzirms r 24 32 s n/a the rms value of the phase current harmonic z. 0xe89a hzwatt r 24 32 s n/a the active power of the harmonic z. 0xe89b hzvar r 24 32 s n/a the reactive power of the harmonic z. 0xe89c hzva r 24 32 s n/a the apparent power of the harmonic z. 0xe89d hzpf r 24 32 s n/a the power factor of the harmonic z. 0xe89e hzvhd r 24 32 s n/a harmonic distortion of the phase voltage harmonic z relative to the fundamental. 0xe89f hzihd r 24 32 s n/a harmonic distortion of the phase current harmonic z relative to the fundamental. 0xe8a0 to 0xe8ff reserved 24 32 reserved. these registers are always 0. 0xe900 hconfig r/w 16 16 u 0x08 harmonic calculations configuration register. see table 54 . 0xe902 apf r 16 16 u n/a phase a power factor. 0xe903 bpf r 16 16 u n/a phase b power factor. 0xe904 cpf r 16 16 u n/a phase c power factor. 0xe905 aperiod r 16 16 u n/a line period on phase a voltage. 0xe906 bperiod r 16 16 u n/a line period on phase b voltage. 0xe907 cperiod r 16 16 u n/a line period on phase c voltage. 0xe908 apnoload r/w 16 16 u 0x0000 no load threshold in the total/ fundamental active power data paths. 0xe909 varnoload r/w 16 16 u 0x0000 no load threshold in the total/ fundamental reactive power data path. 0xe90a vanoload r/w 16 16 u 0x0000 no load threshold in the apparent power data path. 0xe9fe last_add r 16 16 u n/a the address of the re gister successfully accessed during the last read/write operation. 0xe9ff last_rwdata16 r 16 16 u n/a contains the data from the last successful 16-bit register communication. 0xea00 config3 r/w 8 8 u 0x01 configuration register. see table 53 . 0xea01 last_op r 8 8 u n/a indicates the type, read or write, of the last successful read/write operation. 0xea02 wthr r/w 8 8 u 0x03 threshold used in phase total/ fundamental active power data path. 0xea03 varthr r/w 8 8 u 0x03 threshold used in phase total/ fundamental reactive power data path. 0xea04 vathr r/w 8 8 u 0x03 threshold used in phase apparent power data path. 0xea05 to 0xea07 reserved 8 8 reserved. these registers are always 0. 0xea08 hx r/w 8 8 u 3 selects an index of the harmonic monitored by the harmonic computations. 0xea09 hy r/w 8 8 u 5 selects an index of the harmonic monitored by the harmonic computations. 0xea0a hz r/w 8 8 u 7 selects an index of the harmonic monitored by the harmonic
data sheet ade7880 rev. a | page 89 of 104 address register name r/w 1 bit length bit length during communication 2 type 3 default value 4 description computations. 0xea0b to 0xebfe reserved 8 8 reserved. these registers are always 0. 0xebff reserved 8 8 this address can be used in manipulating the ss /hsa pin when spi is chosen as the active port. see the section for details. serial interfaces 0xec00 lpoilvl r/w 8 8 u 0x07 overcurrent threshold used during psm2 mode. see table 55 in which the register is detailed. 0xec01 config2 r/w 8 8 u 0x00 configuration register used during psm1 mode. see table 56 . 1 r is read, and w is write. 2 32 zp = 24- or 20-bit signed or unsigned register that is transmitted as a 32-bit word with 8 or 12 msbs, respectively, padded with 0s. 32 se = 24-bit signed register that is transmitted as a 32-bit word sign extended to 32 bits. 16 zp = 10-bit unsigned register that is transmitted as a 16-bit word with six msbs padded with 0s. 3 u is unsigned register, and s is signed register in twos complement format. 4 n/a is not applicable. table 34. ipeak register (address 0xe500) bit mnemonic default value description 23:0 ipeakval[23:0] 0 these bits contain the peak value determined in the current channel. 24 ipphase[0] 0 when this bit is set to 1, ph ase a current generated ipeakval[23:0] value. 25 ipphase[1] 0 when this bit is set to 1, ph ase b current generated ipeakval[23:0] value. 26 ipphase[2] 0 when this bit is set to 1, ph ase c current generated ipeakval[23:0] value. 31:27 00000 these bits are always 0. table 35. vpeak register (address 0xe501) bit mnemonic default value description 23:0 vpeakval[23:0] 0 these bits contain the peak value determined in the voltage channel. 24 vpphase[0] 0 when this bit is set to 1, ph ase a voltage generated vpeakval[23:0] value. 25 vpphase[1] 0 when this bit is set to 1, ph ase b voltage generated vpeakval[23:0] value. 26 vpphase[2] 0 when this bit is set to 1, phase c voltage generated vpeakval[23:0] value. 31:27 00000 these bits are always 0. table 36. status0 register (address 0xe502) bit mnemonic default value description 0 aehf 0 when this bit is set to 1, it indicates that bit 30 of any one of the total active energy registers (awatthr, bwatthr, or cwatthr) has changed. 1 faehf 0 when this bit is set to 1, it indicates that bit 30 of any one of the fundamental active energy registers, fwatthr, bfwatthr, or cfwatthr, has changed. 2 reserved 0 this bit is always 0. 3 frehf 0 when this bit is set to 1, it indicates that bit 30 of any one of the fundamental reactive energy registers, afvarhr, bfvarhr, or cfvarhr, has changed. 4 vaehf 0 when this bit is set to 1, it indicates th at bit 30 of any one of the apparent energy registers (avahr, bvahr, or cvahr) has changed. 5 lenergy 0 when this bit is set to 1, in line energy accumulation mode, it indicates the end of an integration over an integer number of half line cycles set in the linecyc register. 6 revapa 0 when this bit is set to 1, it indicates that the phase a active power identified by bit 6 (revapsel) in the accmode register (total or fundamental) has changed sign. the sign itself is indicated in bit 0 (awsign) of the phsign register (see table 46 ). 7 revapb 0 when this bit is set to 1, it indicates that the phase b active power identified by bit 6 (revapsel) in the accmode register (total or fundamental) has changed sign. the sign itself is indicated in bit 1 (bwsign) of the phsign register (see table 46 ). 8 revapc 0 when this bit is set to 1, it indicates that the phase c active power identified by bit 6 (revapsel) in the accmode register (total or fundamental) has changed sign. the sign itself is indicated in bit 2 (cwsign) of the phsign register (see table 46 ).
ade7880 data sheet rev. a| page 90 of 104 bit mnemonic default value description 9 revpsum1 0 when this bit is set to 1, it indicates that the sum of all phase powers in the cf1 data path has changed sign. the sign itself is indicated in bit 3 (sum1sign) of the phsign register (see table 46 ). 10 revfrpa 0 when this bit is set to 1, it indicates that the phase a fundamental reactive power has changed sign. the sign itself is indicated in bit 4 (afvarsign) of the phsign register (see table 46 ). 11 revfrpb 0 when this bit is set to 1, it indicates that the phase b fundamental reactive power has changed sign. the sign itself is indicated in bit 5 (bfvarsign) of the phsign register (see table 46 ). 12 revfrpc 0 when this bit is set to 1, it indicates that the phase c fundamental reactive power has changed sign. the sign itself is indicated in bit 6 (cfvarsign) of the phsign register (see table 46 ). 13 revpsum2 0 when this bit is set to 1, it indicates that the sum of all phase powers in the cf2 data path has changed sign. the sign itself is indicated in bit 7 (sum2sign) of the phsign register (see table 46 ). 14 cf1 when this bit is set to 1, it indicates a high-to-low transition has occurred at cf1 pin; that is, an active low pulse has been generated. the bit is set even if the cf1 output is disabled by setting bit 9 (cf1dis) to 1 in the cfmode register. the type of power used at the cf1 pin is determined by bits [2:0] (cf1sel[2:0]) in the cfmode register (see table 44 ). 15 cf2 when this bit is set to 1, it indicates a hi gh-to-low transition has occurred at the cf2 pin; that is, an active low pulse has been generated. the bit is set even if the cf2 output is disabled by setting bit 10 (cf2dis) to 1 in the cfmode register. the type of power used at the cf2 pin is determined by bits[5:3] (cf2sel[2:0]) in the cfmode register (see table 44 ). 16 cf3 when this bit is set to 1, it indicates a high-to-low transition has occurred at cf3 pin; that is, an active low pulse has been generated. the bit is set even if the cf3 output is disabled by setting bit 11 (cf3dis) to 1 in the cfmode register. the type of power used at the cf3 pin is determined by bits[8:6] (cf3sel[2:0]) in the cfmode register (see table 44 ). 17 dready 0 when this bit is set to 1, it indicate s that all periodical (at 8 khz rate) dsp computations have finished. 18 revpsum3 0 when this bit is set to 1, it indicates that the sum of all phase powers in the cf3 data path has changed sign. the sign itself is indicated in bit 8 (sum3sign) of the phsign register (see table 46 ). 19 hready 0 when this bit is set to 1, it indicates th e harmonic block output registers have been updated. if bit 1 (hrcfg) in the hconfig regist er is cleared to 0, this flag is set to 1 every time the harmonic block output registers are updated at 8 khz rate. if bit hrcfg is set to 1, the hready flag is se t to 1 every time the harmonic block output registers are updated at 8 khz rate starting 750 ms after the harmonic block setup . 31:18 reserved 0 0000 0000 0000 reserved. these bits are always 0.
data sheet ade7880 rev. a| page 91 of 104 table 37. status1 register (address 0xe503) bit mnemonic default value description 0 nload 0 when this bit is set to 1, it indicates that at least one phase entered no load condition determined by the total active power and apparent power. the phase is indicated in bits[2:0] (nlphase[x]) in the phnoload register (see table 41 .) 1 fnload 0 when this bit is set to 1, it indicates that at least one phase entered no load condition based on fundamental active and reactive powers. the phase is indicated in bits[5:3] (fnlphase[x]) in the phnoload register (see table 41 ). 2 vanload 0 when this bit is set to 1, it indicates that at least one phase entered no load condition based on apparent power. the phase is indicated in bits[8:6] (vanlphase[x]) in the phnoload register (see table 41 ). 3 zxtova 0 when this bit is set to 1, it indicates a zero crossing on phase a voltage is missing. 4 zxtovb 0 when this bit is set to 1, it indicates a zero crossing on phase b voltage is missing. 5 zxtovc 0 when this bit is set to 1, it indicates a zero crossing on phase c voltage is missing. 6 zxtoia 0 when this bit is set to 1, it indicates a zero crossing on phase a current is missing. 7 zxtoib 0 when this bit is set to 1, it indicates a zero crossing on phase b current is missing. 8 zxtoic 0 when this bit is set to 1, it indicates a zero crossing on phase c current is missing. 9 zxva 0 when this bit is set to 1, it indicates a zero crossing has been detected on phase a voltage. 10 zxvb 0 when this bit is set to 1, it indicates a zero crossing has been detected on phase b voltage. 11 zxvc 0 when this bit is set to 1, it indicates a zero crossing has been detected on phase c voltage. 12 zxia 0 when this bit is set to 1, it indicates a zero crossing has been detected on phase a current. 13 zxib 0 when this bit is set to 1, it indicates a zero crossing has been detected on phase b current. 14 zxic 0 when this bit is set to 1, it indicates a zero crossing has been detected on phase c current. 15 rstdone 1 in case of a software reset command, bit 7 (swrst) is set to 1 in the config register, or a transition from psm1, psm2, or psm3 to psm0, or a hardware reset, this bit is set to 1 at the end of the transition process and after all registers changed value to default. the irq1 pin goes low to signal this mo ment because this interrupt cannot be disabled. 16 sag 0 when this bit is set to 1, it indicates on e of phase voltages entered or exited a sag state. the phase is indicated by bits[14:12] (vsphase[x]) in the phstatus register (see table 40 ). 17 oi 0 when this bit is set to 1, it indicates an overcurrent event has occurred on one of the phases indicated by bits[5:3] (oiphas e[x]) in the phstatus register (see table 40 ). 18 ov 0 when this bit is set to 1, it indicates an overvoltage event has occurred on one of the phases indicated by bits[11:9] (ovphase[x]) in the phstatus register (see table 40 ). 19 seqerr 0 when this bit is set to 1, it indicates a negative-to-positive zero crossing on phase a voltage was not followed by a negative-to-positive zero crossing on phase b voltage but by a negative-to-positive zero crossing on phase c voltage. 20 mismtch 0 when this bit is set to 1, it indicates isumlvl inwv isum >? , where isumlvl is indicated in the isumlvl register. 21 reserved 1 reserved. this bit is always set to 1. 22 reserved 0 reserved. this bit is always set to 0. 23 pki 0 when this bit is set to 1, it indicates that the period used to detect the peak value in the current channel has ended. the ipeak re gister contains the peak value and the phase where the peak has been detected (see table 34 ).
ade7880 data sheet rev. a| page 92 of 104 bit mnemonic default value description 24 pkv 0 when this bit is set to 1, it indicates that the period used to detect the peak value in the voltage channel has ended. vpeak register contains the peak value and the phase where the peak has been detected (see table 35 ). 25 crc 0 when this bit is set to 1, it indicates the ade7880 has computed a different checksum relative to the one computed when the run register was set to 1. 31:26 reserved 000 0000 reserved. these bits are always 0. table 38. mask0 register (address 0xe50a) bit mnemonic default value description 0 aehf 0 when this bit is set to 1, it enables an interrupt when bit 30 of any one of the total active energy registers (awatthr, bwatthr, or cwatthr) changes. 1 faehf 0 when this bit is set to 1, it enables an interrupt when bit 30 of any one of the fundamental active energy registers (afwatthr, bfwatthr, or cfwatthr) changes. 2 reserved 0 this bit does not manage any functionality. 3 frehf 0 when this bit is set to 1, it enables an interrupt when bit 30 of any one of the fundamental reactive energy registers (afvarhr, bfvarhr, or cfvarhr) changes. 4 vaehf 0 when this bit is set to 1, it enables an interrupt when bit 30 of any one of the apparent energy registers (avahr, bvahr, or cvahr) changes. 5 lenergy 0 when this bit is set to 1, in line energy accumulation mode, it enables an interrupt at the end of an integration over an integer number of half line cycles set in the linecyc register. 6 revapa 0 when this bit is set to 1, it enables an interrupt when the phase a active power identified by bit 6 (revapsel) in the accmode register (total or fundamental) changes sign. 7 revapb 0 when this bit is set to 1, it enables an interrupt when the phase b active power identified by bit 6 (revapsel) in the accmode register (total or fundamental) changes sign. 8 revapc 0 when this bit is set to 1, it enables an interrupt when the phase c active power identified by bit 6 (revapsel) in the accmode register (total or fundamental) changes sign. 9 revpsum1 0 when this bit is set to 1, it enables an in terrupt when the sum of all phase powers in the cf1 data path changes sign. 10 revfrpa 0 when this bit is set to 1, it enables an interrupt when the phase a fundamental reactive power changes sign. 11 revfrpb 0 when this bit is set to 1, it enables an interrupt when the phase b fundamental reactive power changes sign. 12 revfrpc 0 when this bit is set to 1, it enables an interrupt when the phase c fundamental reactive power changes sign. 13 revpsum2 0 when this bit is set to 1, it enables an in terrupt when the sum of all phase powers in the cf2 data path changes sign. 14 cf1 when this bit is set to 1, it enables an in terrupt when a high-to-low transition occurs at the cf1 pin, that is an active low pulse is generated. the interrupt can be enabled even if the cf1 output is disabled by se tting bit 9 (cf1dis) to 1 in the cfmode register. the type of power used at the cf1 pin is determined by bits[2:0] (cf1sel[2:0]) in the cfmode register (see table 44 ). 15 cf2 when this bit is set to 1, it enables an in terrupt when a high-to-low transition occurs at cf2 pin, that is an active low pulse is generated. the interrupt may be enabled even if the cf2 output is disabled by se tting bit 10 (cf2dis) to 1 in the cfmode register. the type of power used at the cf2 pin is determined by bits[5:3] (cf2sel[2:0]) in the cfmode register (see table 44 ). 16 cf3 when this bit is set to 1, it enables an in terrupt when a high to low transition occurs at cf3 pin, that is an active low pulse is generated. the interrupt may be enabled even if the cf3 output is disabled by se tting bit 11 (cf3dis) to 1 in the cfmode register. the type of power used at the cf3 pin is determined by bits[8:6] (cf3sel[2:0]) in the cfmode register (see table 44 ). 17 dready 0 when this bit is set to 1, it enables an interrupt when all periodical (at 8 khz rate) dsp computations finish.
data sheet ade7880 rev. a| page 93 of 104 bit mnemonic default value description 18 revpsum3 0 when this bit is set to 1, it enables an in terrupt when the sum of all phase powers in the cf3 data path changes sign. 19 hready 0 when this bit is set to 1, it enables an interrupt when the harmonic block output registers have been updated. if bit 1 (hrcfg ) in hconfig register is cleared to 0, the interrupt is triggered every time the harmonic calculations are updated at 8 khz rate. if bit hrcfg is set to 1, the interr upt is triggered every time the harmonic calculations are updated at 8 khz rate starting 750 ms after the harmonic block setup. 31:19 reserved 00 0000 0000 0000 reserved. these bits do not manage any functionality. table 39. mask1 register (address 0xe50b) bit mnemonic default value description 0 nload 0 when this bit is set to 1, it enables an interrupt when at least one phase enters no load condition determined by the total active power and vnom based apparent power. 1 fnload 0 when this bit is set to 1, it enables an interrupt when at least one phase enters no load condition based on fundamental active and reactive powers. 2 vanload 0 when this bit is set to 1, it enables an interrupt when at least one phase enters no load condition based on apparent power. 3 zxtova 0 when this bit is set to 1, it enables an interrupt when a zero crossing on phase a voltage is missing. 4 zxtovb 0 when this bit is set to 1, it enables an interrupt when a zero crossing on phase b voltage is missing. 5 zxtovc 0 when this bit is set to 1, it enables an interrupt when a zero crossing on phase c voltage is missing. 6 zxtoia 0 when this bit is set to 1, it enables an interrupt when a zero crossing on phase a current is missing. 7 zxtoib 0 when this bit is set to 1, it enables an interrupt when a zero crossing on phase b current is missing. 8 zxtoic 0 when this bit is set to 1, it enables an interrupt when a zero crossing on phase c current is missing. 9 zxva 0 when this bit is set to 1, it enables an in terrupt when a zero crossing is detected on phase a voltage. 10 zxvb 0 when this bit is set to 1, it enables an in terrupt when a zero crossing is detected on phase b voltage. 11 zxvc 0 when this bit is set to 1, it enables an in terrupt when a zero crossing is detected on phase c voltage. 12 zxia 0 when this bit is set to 1, it enables an in terrupt when a zero crossing is detected on phase a current. 13 zxib 0 when this bit is set to 1, it enables an in terrupt when a zero crossing is detected on phase b current. 14 zxic 0 when this bit is set to 1, it enables an in terrupt when a zero crossing is detected on phase c current. 15 rstdone 0 because the rstdone interrupt cannot be disabled, this bit does not have any functionality attached. it can be set to 1 or cleared to 0 without having any effect. 16 sag 0 when this bit is set to 1, it enables an interrupt when one of the phase voltages entered or exited a sag state. the phase is indicated by bits[14:12] (vsphase[x]) in the phstatus register (see table 40 ). 17 oi 0 when this bit is set to 1, it enables an interrupt when an overcurrent event occurs on one of the phases indicated by bits[5 :3] (oiphase[x]) in the phstatus register (see table 40 ). 18 ov 0 when this bit is set to 1, it enables an interrupt when an overvoltage event occurs on one of the phases indicated by bits[ 11:9] (ovphase[x]) in the phstatus register (see table 40 ). 19 seqerr 0 when this bit is set to 1, it enables an interrupt when a negative-to-positive zero crossing on phase a voltage is not followe d by a negative-to-positive zero crossing on phase b voltage, but by a negative-to-positive zero crossing on phase c voltage.
ade7880 data sheet rev. a| page 94 of 104 bit mnemonic default value description 20 mismtch 0 when this bit is set to 1, it enables an interrupt when isumlvl inwv isum >? is greater than the value indicated in isumlvl register. 22:21 reserved 00 reserved. these bits do not manage any functionality. 23 pki 0 when this bit is set to 1, it enables an in terrupt when the period used to detect the peak value in the current channel has ended. 24 pkv 0 when this bit is set to 1, it enables an in terrupt when the period used to detect the peak value in the voltage channel has ended. 25 crc 0 when this bit is set to 1, it enables an interrupt when the late st checksum value is different from the checksum value computed when run register was set to 1. 31:26 reserved 000 0000 reserved. these bits do not manage any functionality. table 40. phstatus register (address 0xe600) bit mnemonic default value description 2:0 reserved 000 reserved. these bits are always 0. 3 oiphase[0] 0 when this bit is set to 1, phase a current generates bit 17 (oi) in the status1 register. 4 oiphase[1] 0 when this bit is set to 1, phase b cu rrent generates bit 17 (oi) in the status1 register. 5 oiphase[2] 0 when this bit is set to 1, phase c current generates bit 17 (oi) in the status1 register. 8:6 reserved 000 reserved. these bits are always 0. 9 ovphase[0] 0 when this bit is set to 1, phase a vo ltage generates bit 18 (ov) in the status1 register. 10 ovphase[1] 0 when this bit is set to 1, phase b vo ltage generates bit 18 (ov) in the status1 register. 11 ovphase[2] 0 when this bit is set to 1, phase c voltage generates bit 18 (ov) in the status1 register. 12 vsphase[0] 0 0: phase a voltage is above saglvl level for sagcyc half line cycles 1: phase a voltage is below saglvl level for sagcyc half line cycles when this bit is switches from 0 to 1 or from 1 to 0, the phase a voltage generates bit 16 (sag) in the status1 register. 13 vsphase[1] 0 0: phase b voltage is above saglvl level for sagcyc half line cycles 1: phase b voltage is below saglvl level for sagcyc half line cycles when this bit is switches from 0 to 1 or from 1 to 0, the phase b voltage generates bit 16 (sag) in the status1 register. 14 vsphase[2] 0 0: phase c voltage is above saglvl level for sagcyc half line cycles 1: phase c voltage is below saglvl level for sagcyc half line cycles when this bit is switches from 0 to 1 or from 1 to 0, the phase c voltage generates bit 16 (sag) in the status1 register. 15 reserved 0 reserved. this bit is always 0. table 41. phnoload register (address 0xe608) bit mnemonic default value description 0 nlphase[0] 0 0: phase a is out of no load condition dete rmined by the phase a total active power and apparent power. 1: phase a is in no load condition determined by phase a total active power and apparent power. bit set together with bit 0 (nload) in the status1 register. 1 nlphase[1] 0 0: phase b is out of no load condition determined by the phase b total active power and apparent power. 1: phase b is in no load condition determined by the phase b total active power and apparent power. bit set together with bit 0 (nload) in the status1 register. 2 nlphase[2] 0 0: phase c is out of no load condition dete rmined by the phase c total active power and apparent power. 1: phase c is in no load condition determined by the phase c total active power and apparent power. bit set together with bit 0 (nload) in the status1 register. 3 fnlphase[0] 0 0: phase a is out of no load condit ion based on fundamental active/reactive powers. 1: phase a is in no load condition based on fundamental active/reactive powers. this bit is set together with bit 1 (fnload) in status1.
data sheet ade7880 rev. a| page 95 of 104 bit mnemonic default value description 4 fnlphase[1] 0 0: phase b is out of no load condit ion based on fundamental active/reactive powers. 1: phase b is in no load condition based on fundamental active/reactive powers. this bit is set together with bit 1 (fnload) in status1. 5 fnlphase[2] 0 0: phase c is out of no load condit ion based on fundamental active/reactive powers. 1: phase c is in no load condition based on fundamental active/reactive powers. this bit is set together with bit 1 (fnload) in status1. 6 vanlphase[0] 0 0: phase a is out of no load condition based on apparent power. 1: phase a is in no load condition based on apparent power. bit set together with bit 2 (vanload) in the status1 register. 7 vanlphase[1] 0 0: phase b is out of no load condition based on apparent power. 1: phase b is in no load condition based on apparent power. bit set together with bit 2 (vanload) in the status1 register. 8 vanlphase[2] 0 0: phase c is out of no load condition based on apparent power. 1: phase c is in no load condition based on apparent power. bit set together with bit 2 (vanload) in the status1 register. 15:9 reserved 000 0000 reserved. these bits are always 0. table 42. compmode register (address 0xe60e) bit mnemonic default value description 0 termsel1[0] 1 setting all termsel1[2:0] to 1 signifies the sum of all three phases is included in the cf1 output. phase a is included in the cf1 outputs calculations. 1 termsel1[1] 1 phase b is included in the cf1 outputs calculations. 2 termsel1[2] 1 phase c is included in the cf1 outputs calculations. 3 termsel2[0] 1 setting all termsel2[2:0] to 1 signifies the sum of all three phases is included in the cf2 output. phase a is included in the cf2 outputs calculations. 4 termsel2[1] 1 phase b is included in the cf2 outputs calculations. 5 termsel2[2] 1 phase c is included in the cf2 outputs calculations. 6 termsel3[0] 1 setting all termsel3[2:0] to 1 signifies the sum of all three phases is included in the cf3 output. phase a is included in the cf3 outputs calculations. 7 termsel3[1] 1 phase b is included in the cf3 outputs calculations. 8 termsel3[2] 1 phase c is included in the cf3 outputs calculations. 10:9 anglesel[1:0] 00 00: the angles between phas e voltages and phase currents are measured. 01: the angles between phase voltages are measured. 10: the angles between phase currents are measured. 11: no angles are measured. 11 vnomaen 0 when this bit is 0, the apparent power on phase a is computed regularly. when this bit is 1, the apparent power on ph ase a is computed usin g vnom register instead of regular measured rms phase voltage. 12 vnomben 0 when this bit is 0, the apparent power on phase b is computed regularly. when this bit is 1, the apparent power on phas e b is computed using vno m register instead of regular measured rms phase voltage. 13 vnomcen 0 when this bit is 0, the apparent power on phase c is computed regularly. when this bit is 1, the apparent power on phas e c is computed using vno m register instead of regular measured rms phase voltage. 14 selfreq 0 when the ade7880 is connected to 50 hz networks, this bit should be cleared to 0 (default value). when the ade7880 is connected to 60 hz networks, this bit should be set to 1. 15 reserved 0 this bit is 0 by default an d it does not manage any functionality.
ade7880 data sheet rev. a| page 96 of 104 table 43. gain register (address 0xe60f) bit mnemonic default value description phase currents gain selection. 000: gain = 1. 001: gain = 2. 010: gain = 4. 011: gain = 8. 100: gain = 16. 2:0 pga1[2:0] 000 101, 110, 111: reserved. when set, the ade7880 behaves like pga1[2:0] = 000. 5:3 pga2[2:0] 000 neutral current gain selection. 000: gain = 1. 001: gain = 2. 010: gain = 4. 011: gain = 8. 100: gain = 16. 101, 110, 111: reserved. when set, the ade7880 behaves like pga2[2:0] = 000. phase voltages gain selection. 000: gain = 1. 001: gain = 2. 010: gain = 4. 011: gain = 8. 100: gain = 16. 8:6 pga3[2:0] 000 101, 110, 111: reserved. when set, the ade7880 behaves like pga3[2:0] = 000. 15:9 reserved 000 0000 reserved. these bits do not manage any functionality. table 44. cfmode register (address 0xe610) bit mnemonic default value description 000: the cf1 frequency is proportional to the sum of total active powers on each phase identified by bits[2:0] (termsel1[x]) in the compmode register. 010: the cf1 frequency is proportional to the sum of apparent powers on each phase identified by bits[2:0] (termsel1[x]) in the compmode register. 011: the cf1 frequency is proportional to the sum of fundamental active powers on each phase identified by bits[2:0] (termsel1[x]) in the compmode register. 100: the cf1 frequency is proportional to the sum of fundamental reactive powers on each phase identified by bits[2:0] (termsel1[x]) in the compmode register. 2:0 cf1sel[2:0] 000 001, 101, 110, 111: reserved. 000: the cf2 frequency is proportional to the sum of total active powers on each phase identified by bits[5:3] (termsel2[x]) in the compmode register. 010: the cf2 frequency is proportional to the sum of apparent powers on each phase identified by bits[5:3] (termsel2[x]) in the compmode register. 011: the cf2 frequency is proportional to the sum of fundamental active powers on each phase identified by bits[5:3] (termsel2[x]) in the compmode register. 100: the cf2 frequency is proportional to the sum of fundamental reactive powers on each phase identified by bits[5:3] (termsel2[x]) in the compmode register. 5:3 cf2sel[2:0] 100 001, 101,110,111: reserved.
data sheet ade7880 rev. a| page 97 of 104 bit mnemonic default value description 000: the cf3 frequency is proportional to the sum of total active powers on each phase identified by bits[8:6] (termsel3[x]) in the compmode register. 010: the cf3 frequency is proportional to the sum of apparent powers on each phase identified by bits[8:6] (termsel3[x]) in the compmode register. 011: cf3 frequency is proportional to the sum of fundamental active powers on each phase identified by bits [8:6] (termsel3[x]) in the compmode register. 100: cf3 frequency is proportional to the sum of fundamental reactive powers on each phase identified by bits[8:6] (termsel3[x]) in the compmode register. 8:6 cf3sel[2:0] 010 001, 101,110,111: reserved. 9 cf1dis 1 when this bit is set to 1, the cf1 outp ut is disabled. the respective digital to frequency converter remains enabled even if cf1dis = 1. when this bit is set to 0, the cf1 output is enabled. 10 cf2dis 1 when this bit is set to 1, the cf2 outp ut is disabled. the respective digital to frequency converter remains enabled even if cf2dis = 1. when this bit is set to 0, the cf2 output is enabled. 11 cf3dis 1 when this bit is set to 1, the cf3 outp ut is disabled. the respective digital to frequency converter remains enabled even if cf3dis = 1. when this bit is set to 0, the cf3 output is enabled. 12 cf1latch 0 when this bit is set to 1, the content of the corresponding energy registers is latched when a cf1 pulse is generated. see the synchronizing energy registers with cfx outputs section. 13 cf2latch 0 when this bit is set to 1, the content of the corresponding energy registers is latched when a cf2 pulse is generated. see the synchronizing energy registers with cfx outputs section. 14 cf3latch 0 when this bit is set to 1, the content of the corresponding energy registers is latched when a cf3 pulse is generated. see the synchronizing energy registers with cfx outputs section. 15 reserved 0 reserved. this bit does not manage any functionality. table 45. aphcal, bphcal, cphcal registers (address 0xe614, address 0xe615, address 0xe616) bit mnemonic default value description if current channel compensation is necessary, these bits can vary only between 0 and 383. if voltage channel compensation is necessary, these bits can vary only between 512 and 575. if the phcalval bits are set with numbers between 384 and 511, the compensation behaves like phcalval set between 256 and 383. 9:0 phcalval 0000000000 if the phcalval bits are set with numbers between 576 and 1023, the compensation behaves like phcalval bits set between 384 and 511. 15:10 reserved 000000 reserved. these bits do not manage any functionality. table 46. phsign register (address 0xe617) bit mnemonic default value description 0: if the active power identified by bit 6 (revapsel) in the accmode register (total of fundamental) on phase a is positive. 0 awsign 0 1: if the active power identified by bit 6 (revapsel) in the accmode register (total of fundamental) on phase a is negative. 1 bwsign 0 0: if the active power identified by bit 6 (revapsel) in the accmode register (total of fundamental) on phase b is positive. 1: if the active power identified by bit 6 (revapsel) in the accmode register (total of fundamental) on phase b is negative. 2 cwsign 0 0: if the active power identified by bit 6 (revapsel) in the accmode register (total of fundamental) on phase c is positive. 1: if the active power identified by bit 6 (revapsel) bit in the accmode register (total of fundamental) on phase c is negative.
ade7880 data sheet rev. a| page 98 of 104 bit mnemonic default value description 3 sum1sign 0 0: if the sum of all phase po wers in the cf1 data path is positive. 1: if the sum of all phase powers in the cf1 da ta path is negative. phase powers in the cf1 data path are identified by bits[2:0] (termsel1[x]) of the compmode register and by bits[2:0] (cf1sel[x]) of the cfmode register. 4 afvarsign 0 0: if the fundamental reactive power on phase a is positive. 1: if the fundamental reactive power on phase a is negative. 5 bfvarsign 0 0: if the fundamental reactive power on phase b is positive. 1: if the fundamental reactive power on phase b is negative. 6 cfvarsign 0 0: if the fundamental reactive power on phase c is positive. 1: if the fundamental reactive power on phase c is negative. 7 sum2sign 0 0: if the sum of all phase po wers in the cf2 data path is positive. 1: if the sum of all phase powers in the cf2 da ta path is negative. phase powers in the cf2 data path are identified by bits[5:3] (termsel2[x]) of the compmode register and by bits[5:3] (cf2sel[x]) of the cfmode register. 8 sum3sign 0 0: if the sum of all phase po wers in the cf3 data path is positive. 1: if the sum of all phase powers in the cf3 da ta path is negative. phase powers in the cf3 data path are identified by bits[8:6] (termsel3[x]) of the compmode register and by bits[8:6] (cf3sel[x]) of the cfmode register. 15:9 reserved 000 0000 reserved. these bits are always 0. table 47. config register (address 0xe618) bit mnemonic default value description 0 inten 0 this bit manages the integrators in the phase current channels. if inten=0, then the integrators in the phase current channels are always disabled. if inten=1, then the integrators in the phase currents channels are enabled. the neutral current channel integrator is mana ged by bit 3 (ininten ) of config3 register. 1 reserved 1 reserved. this bit should be maintained at 1 for proper operation. 2 cf2dis 0 when this bit is cleared to 0, the cf2 functionality is chosen at cf2/hready pin. when this bit is set to 1, the hready fu nctionality is chosen at cf2/hready pin. 3 swap 0 when this bit is set to 1, the voltage channe l outputs are swapped with the current channel outputs. thus, the current channel information is present in the voltage channel registers and vice versa. 4 mod1short 0 when this bit is set to 1, the voltage channel adcs behave as if the voltage inputs were put to ground. 5 mod2short 0 when this bit is set to 1, the current channel adcs behave as if the voltage inputs were put to ground. 6 hsdcen 0 when this bit is set to 1, the hsdc serial port is enabled and hsclk functionality is chosen at cf3/hsclk pin. when this bit is cleared to 0, hsdc is disabled and cf3 functionality is chosen at cf3/hsclk pin. 7 swrst 0 when this bit is set to 1, a software reset is initiated. these bits decide what phase voltage is cons idered together with phase a current in the power path. 00 = phase a voltage. 01 = phase b voltage. 10 = phase c voltage. 9:8 vtoia[1:0] 00 11 = reserved. when set, the ade7880 behaves like vtoia[1:0] = 00. these bits decide what phase voltage is considered together with phase b current in the power path. 00 = phase b voltage. 01 = phase c voltage. 10 = phase a voltage. 11:10 vtoib[1:0] 00 11 = reserved. when set, the ade7880 behaves like vtoib[1:0] = 00.
data sheet ade7880 rev. a| page 99 of 104 bit mnemonic default value description these bits decide what phase voltage is cons idered together with phase c current in the power path. 00 = phase c voltage. 01 = phase a voltage. 10 = phase b voltage. 13:12 vtoic[1:0] 00 11 = reserved. when set, the ade7880 behaves like vtoic[1:0] = 00. 15:14 reserved reserved. table 48. mmode register (address 0xe700) bit mnemonic default value description 1:0 reserved reserved. 2 peaksel[0] 1 peaksel[2:0] bits can all be set to 1 simultan eously to allow peak detection on all three phases simultaneously. if more than one peakse l[2:0] bits are set to 1, then the peak measurement period indicated in the peakcyc re gister decreases accordingly because zero crossings are detected on more than one phase. when this bit is set to 1, phase a is selected for the voltage and current peak registers. 3 peaksel[1] 1 when this bit is set to 1, phase b is selected for the voltage and current peak registers. 4 peaksel[2] 1 when this bit is set to 1, phase c is selected for the voltage and current peak registers. 7:5 reserved 000 reserved. these bits do not manage any functionality. table 49. accmode register (address 0xe701) bit mnemonic default value description 00: signed accumulation mode of the total and fundamental active powers. the total and fundamental active energy registers and the cfx pulses are generated in the same way. 01: positive only accumulation mode of the total and fundamental active powers. in this mode, although the total and fundamental ac tive energy registers are accumulated in positive only mode, the cfx pulses are generated in signed accumulation mode. 10: reserved. when set, the device behaves like wattacc[1:0] = 00. 1:0 wattacc[1:0] 00 11: absolute accumulation mode of the total and fundamental active powers. the total and fundamental energy registers and the cfx pulses are generated in the same way. 00: signed accumulation of the fundamental reactive powers. the fundamental reactive energy registers and the cfx pulses are generated in the same way. 01: reserved. when set, the device behaves like varacc[1:0] = 00. 10: the fundamental reactive power is accu mulated, depending on the sign of the fundamental active power: if the active power is positive, the reactive power is accumulated as is, whereas if the active power is negative, the reactive power is accumulated with reversed sign. in this mode, although the total and fundamental reactive energy registers are accumulated in absolute mode, the cfx pulses are generated in signed accumulation mode. 3:2 varacc[1:0] 00 11: absolute accumulation mode of the fundamental reactive powers. in this mode, although the total and fundamental reactive en ergy registers are accu mulated in absolute mode, the cfx pulses are generated in signed accumulation mode. these bits select the inputs to the energy accumula tion registers. ia, ib, and ic are ia, ib, and ic shifted respectively by ?90. see table 50 . 00: 3-phase four wires with three voltage sensors. 01: 3-phase three wires delta connection. in this mode, bvrms register contains the rms value of va-vc. 10: 3-phase four wires with two voltage sensors. 5:4 consel[1:0] 00 11: 3-phase four wires delta connection.
ade7880 data sheet rev. a| page 100 of 104 bit mnemonic default value description 6 revapsel 0 0: the total active power on each phase is used to trigger a bit in the status0 register as follows: on phase a triggers bit 6 (revapa), on phase b triggers bit 7 (revapb), and on phase c triggers bit 8 (revapc). 1: the fundamental active power on each phase is used to trigger a bit in the status0 register as follows: on phase a triggers bit 6 (revapa), on phase b triggers bit 7 (revapb), and on phase c triggers bit 8 (revapc). 7 reserved 1 reserved. this bit does not manage any functionality. table 50. consel[1:0] bits in energy registers 1 energy registers consel[1:0] = 00 consel[1 :0] = 01 consel[1:0] = 10 consel[1:0] = 11 awat thr, afwat thr va ia va ia va ia va ia bwatthr, bfwatthr vb ib vb = va C vc vb = ?va C vc vb = ?va vb ib 1 vb ib vb ib cwatthr, cfwatthr vc ic vc ic vc ic vc ic avarhr, afvarhr va ia va ia va ia va ia bvarhr, bfvarhr vb ib vb = va C vc vb = ?va C vc vb = ?va vb ib 1 vb ib vb ib cvarhr, cfvarhr vc ic vc ic vc ic vc ic avahr va rms ia rms va rms ia rms va rms ia rms va rms ia rms bvahr vb rms ib rms vb rms ib rms vb rms ib rms vb rms ib rms vb = va C vc 1 cvahr vc rms ic rms vc rms ic rms vc rms ic rms vc rms ic rms 1 in a 3-phase three wire ca se (consel[1:0] = 01), the ade7880 computes the rms value of the line voltage between phase a and and phase c and stores the result into bvrms register (see the voltage rms in 3-phase thre e wire delta configurations section). consequently, the ade7880 computes powers associated with phase b that do not have physical meaning. to avoid any errors in the frequency output pins cf1, cf2 or cf3 related to the powers associated with phase b, disable the contribution of phase b to the energy to frequency converters by setting bits termsel1[1], or termsel2[1], or termsel3[1] to 0 in the compmode register (see the energy-to-frequency conversion section). table 51. lcycmode register (address 0xe702) bit mnemonic default value description 0 lwatt 0 0: the watt-hour accumulation registers (awatthr, bwatthr, cwatthr, afwatthr, bfwatthr, and cfwatthr) are placed in regular accumulation mode. 1: the watt-hour accumulation registers (awatthr, bwatthr, cwatthr, afwatthr, bfwatthr, and cfwatthr) are placed into line cycle accumulation mode. 1 lvar 0 0: the var-hour accumulation registers (afvarhr, bfvarhr, and cfvarhr) are placed in regular accumulation mode. 1: the var-hour accumulation registers (afvarhr , bfvarhr, and cfvarhr) are placed into line- cycle accumulation mode. 2 lva 0 0: the va-hour accumulation registers (avahr , bvahr, and cvahr) are placed in regular accumulation mode. 1: the va-hour accumulation registers (avahr, bvahr, and cvahr) are placed into line-cycle accumulation mode. 3 zxsel[0] 1 0: phase a is not selected for zero-cro ssings counts in the line cycle accumulation mode. 1: phase a is selected for zero-crossings counts in the line cycle accumulation mode. if more than one phase is selected for zero-crossing detection, the accumulation time is shortened accordingly. 4 zxsel[1] 1 0: phase b is not selected for zero-crossings counts in the line cycle accumulation mode. 1: phase b is selected for zero-crossings counts in the line cycle accumulation mode. 5 zxsel[2] 1 0: phase c is not selected for zero-crossings counts in the line cycle accumulation mode. 1: phase c is selected for zero-crossings counts in the line cycle accumulation mode. 6 rstread 1 0: read-with-reset of all energy registers is disa bled. clear this bit to 0 when bits[2:0] (lwatt, lvar, and lva) are set to 1. 1: enables read-with-reset of all xwatthr, xv arhr, xvahr, xfwatthr, and xfvarhr registers. this means a read of those registers resets them to 0.
data sheet ade7880 rev. a| page 101 of 104 bit mnemonic default value description 7 pfmode 0 0: power factor calculation uses instantaneous values of various phase powers used in its expression. 1: power factor calculation uses phase energies values calculated using line cycle accumulation mode. bits lwatt and lva in lcycmode register must be enabled for the power factors to be computed correctly. the update rate of the power factor measurement in this case is the integral number of half line cycles that ar e programmed into the linecyc register. table 52. hsdc_cfg register (address 0xe706) bit mnemonic default value description 0 hclk 0 0: hsclk is 8 mhz. 1: hsclk is 4 mhz. 1 hsize 0 0: hsdc transmits the 32-bit registers in 32-bit packages, most significant bit first. 1: hsdc transmits the 32-bit registers in 8-bit packages, most significant bit first. 2 hgap 0 0: no gap is introduced between packages. 1: a gap of seven hclk cycles is introduced between packages. 4:3 hxfer[1:0] 00 00 = hsdc transmits sixteen 32-bit words in the following order: iawv, vawv, ibwv, vbwv, icwv, vcwv, inwv, ava, bva, cva, awatt, bwatt, cwatt, afvar, bfvar, and cfvar. 01 = hsdc transmits seven instantaneous valu es of currents and voltages: iawv, vawv, ibwv, vbwv, icwv, vcwv, and inwv. 10 = hsdc transmits nine instanta neous values of phase powers: ava, bva, cva, awatt, bwat t, cwatt, afvar, bfvar, and cfvar. 11 = reserved. if set, the ade7880 behaves as if hxfer[1:0] = 00. 5 hsapol 0 0: ss /has output pin is active low. 1: ss /hsa output pin is active high. 7:6 reserved 00 reserved. these bits do not manage any functionality. table 53. config3 register (address 0xea00) bit mnemonic default value description 0 hpfen 1 when hpfen = 1, then all high-pass filters in voltage and current channels are enabled. when hpfen = 0, then all high-pass filters are disabled. 1 lpfsel 0 when lpfsel = 0, the lpf in the total active po wer data path introduces a settling time of 650 ms. when lpfsel = 1, the lpf in the total active po wer data path introduces a settling time of 1300 ms. 2 insel 0 when insel = 0, the register nirms contains the rms value of the neutral current. when insel = 1, the register nirms contains the rms value of isum, the instantaneous value of the sum of all 3 phase currents, ia, ib, and ic. 3 ininten 0 this bit manages the integrat or in the neutral current channel. if ininten = 0, then the integrator in the neutral current channel is disabled. if inintdis = 1, then the integrator in the neutral channel is enabled. the integrators in the phase currents channels are managed by bit 0 (inten) of config register. 4 reserved 0 reserved. this bit should be maintained at 0 for proper operation. 7:5 reserved 000 reserved. these bits do not manage any functionality.
ade7880 data sheet rev. a| page 102 of 104 table 54. hconfig register (address 0xe900) bit mnemonic default value description 0 hrcfg 0 when this bit is cleared to 0, the bit 19 (hr eady) interrupt in mask0 register is triggered after a certain delay period. the delay period is set by bits hstime. the update frequency after the settling time is determined by bits hrate. when this bit is set to 1, the bit 19 (hready) in terrupt in mask0 register is triggered starting immediately after the harmonic calculations bloc k has been setup. the update frequency is determined by bits hrate. 2:1 hphase 00 these bits decide what phase or neutral is analyzed by the harmon ic calculations block. 00 = phase a voltage and current. 01 = phase b voltage and current. 10 = phase c voltage and current. 11 = neutral current. 4:3 hstime 01 these bits decide the delay period after which, if hrcfg bit is set to 1, bit 19 (hready) interrupt in mask0 register is triggered. 00 = 500 ms. 01 = 750 ms. 10 = 1000 ms. 11 = 1250 ms. 7:5 hrate 000 these bits manage the upda te rate of the harmonic registers. 000 = 125 sec (8 khz rate). 001 = 250 sec (4 khz rate). 010 = 1 ms (1 khz rate). 011 = 16 ms (62.5 hz rate). 100 = 128 ms (7.8125 hz rate). 101 = 512 ms (1.953125 hz rate). 110 = 1.024 sec (0.9765625 hz rate). 111 = harmonic calculations disabled. 9:8 actphsel 00 these bits select the phase voltag e used as time base for harmonic calculations. 00 = phase a voltage. 01 = phase b voltage. 10 = phase c voltage. 11 = reserved. if selected, phase c voltage is used. 15:10 reserved 0 reserved. these bits do not manage any functionality. table 55. lpoilvl register (address 0xec00) bit mnemonic default value description 2:0 lpoil[2:0] 111 threshold is put at a value corr esponding to full scale multiplied by lpoil/8. 7:3 lpline[4:0] 00000 the measurement period is (lpline + 1)/50 seconds. table 56. config2 register (address 0xec01) bit mnemonic default value description 0 extrefen 0 when this bit is 0, it signifies that the internal voltage reference is used in the adcs. when this bit is 1, an external reference is connected to the pin 17 ref in/out . 1 i2c_lock 0 when this bit is 0, the ss /hsa pin can be toggled three times to activate the spi port. if i 2 c is the active serial port, this bit must be set to 1 to lock it in. from this moment on, toggling of the ss /hsa pin and an eventual switch into using the spi port is no longer possible. if spi is the active serial port, any write to config2 register locks the port . from this moment on, a switch into using i 2 c port is no longer possible. once locked, the serial port choice is maintained when the changes psmx power modes. ade7880 7:2 reserved 0 reserved. these bits do not manage any functionality.
data sheet ade7880 rev. a| page 103 of 104 outline dimensions 05-06-2011-a 0.50 bsc bottom view top view pin 1 indicator exposed pad p i n 1 i n d i c a t o r seating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.23 0.18 6.10 6.00 sq 5.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.25 min 4.45 4.30 sq 4.25 compliant to jedec standards mo-220-wjjd. 40 1 11 20 21 30 31 10 figure 111. 40-lead lead frame chip scale package [lfcsp_wq] 6 mm 6 mm body, very very thin quad (cp-40-10) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ade7880 acpz ?40c to +85c 40-lead lfcsp_wq cp-40-10 ade7880 acpz-rl ?40c to +85c 40-lead lfcsp_wq, 13 tape and reel cp-40-10 eval- ade7880 ebz evaluation board 1 z = rohs compliant part.
ade7880 data sheet rev. a| page 104 of 104 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2011C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10193-0-3/12(a)

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